Re: [USRP-users] X310 Register's Memory Capability

2018-06-08 Thread Derek Kozel via USRP-users
I'm not an FPGA expert by a long shot so I'm afraid I can't point at anything specific. The DRAM FIFO may offer some inspiration or the SRAM FIFOs. How and where you need to access the data will influence what the best solution is. Can you say anything more about your application? That would likely

Re: [USRP-users] X310 Register's Memory Capability

2018-06-08 Thread shachar J. brown via USRP-users
Thank you Jonathon and Derek, Derek, you are absolutely correct. I'm not planning on storing filter taps but rather generic data, and lots of it. Likewise, I'm planning on changing the data on the run. What's your suggestion for the most efficient way on doing this? (By efficient, I mean a way tha

Re: [USRP-users] X310 Register's Memory Capability

2018-06-07 Thread Derek Kozel via USRP-users
Hi Steve, As an addon to Jonathon's email, you haven't actually said that you want to store filter taps. If you are storing generic data then the embedded regs are unlikely to be helpful for you because you are not going to be using the data with DSP48s. Regards, Derek On Fri, Jun 8, 2018 at 6:0

Re: [USRP-users] X310 Register's Memory Capability

2018-06-07 Thread Jon Pendlum via USRP-users
Hi Steve, USE_EMBEDDED_REGS_COEFFS means that the filter will attempt to infer the DSP48's embedded registers (specifically register B) for storing coefficients. You should refer to Xilinx's DSP48 design doc https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf. Using

Re: [USRP-users] X310 Register's Memory Capability

2018-06-07 Thread shachar J. brown via USRP-users
After examining the files in depth, I realized I need some help understanding core concepts in FPGA programming: In "axi_fir_filter.v" there is a parameter named "USE_EMBEDDED_REGS_COEFFS", and explained in comment: " Reduce register usage by only using embedded registers in DSP slices". - What i

Re: [USRP-users] X310 Register's Memory Capability

2018-06-07 Thread Nick Foster via USRP-users
It's going to depend on how much block RAM the image is already using, and how much more you can use while still getting the image to route. The easiest way to find out will be to try it. On Thu, Jun 7, 2018, 9:14 AM shachar J. brown wrote: > Thanks Nick, that's an excellent example. > Do you kn

Re: [USRP-users] X310 Register's Memory Capability

2018-06-07 Thread shachar J. brown via USRP-users
Thanks Nick, that's an excellent example. Do you know what are the memory size restrictions of the configuration data? On Thu, Jun 7, 2018 at 10:50 AM, Nick Foster wrote: > Look at the RFNoC FIR filter block for a good example of pushing > configuration data into a block via the settings bus. >

Re: [USRP-users] X310 Register's Memory Capability

2018-06-07 Thread Nick Foster via USRP-users
Look at the RFNoC FIR filter block for a good example of pushing configuration data into a block via the settings bus. On Thu, Jun 7, 2018, 8:25 AM shachar J. brown via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi all, > > I'm working on an X310. > > I have large data (tables of 1-3 K of

[USRP-users] X310 Register's Memory Capability

2018-06-07 Thread shachar J. brown via USRP-users
Hi all, I'm working on an X310. I have large data (tables of 1-3 K of variables) I would like to insert into the FPGA's memory registers while running. How much space is available in the FPGA? Seemingly, the Address for the "set_register" is only 8 bits long, and the first 128 addresses are rese