r.mak
Adam Parower
From: Jon Pendlum
Sent: Monday, January 29, 2018 7:52:47 PM
To: Adam Parower
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] RFNoC: Synthesizing a block containing modules from
uhd-fpga
Hi Adam,
Can you post your testbench makefile?
Jonathon
On
Hi Adam,
Can you post your testbench makefile?
Jonathon
On Jan 10, 2018 5:07 PM, "Adam Parower via USRP-users" <
usrp-users@lists.ettus.com> wrote:
> Hello everyone,
>
>
> I am trying to create a custom RFNoC block that is similar to the built-in
> DUC block. As such, it depends on the cordic_t
Hello everyone,
I am trying to create a custom RFNoC block that is similar to the built-in DUC
block. As such, it depends on the cordic_timed, axi_rate_change, and duc
modules defined in uhd-fpga/usrp3/lib/rfnoc. When I attempt to run the
testbench for my block, Vivado fails in synthesis. Whil
