Hi Arnika,
Good catch. It looks like the commit here changed HLS generation:
https://github.com/EttusResearch/fpga/commit/615d9b8eeb94ee2d19c3b1e7aa526d4999495e05
I tested the addsub_hls testbench, which runs fine. However, it seems as
though the devices (e300, n3xx, x310) have no process to incl
Hi all,
After updating fpga source to most recent master branch, I noticed that rfnoc
blocks, which uses HLS generated IP cores, are no longer synthesizing with the
project. Furthermore, viv_hls_ip_builder is not starting at all. I think that
the reason of this problem is missing HLS targets in
