Re: [USRP-users] BRAM usage of the X300/X310 design

2018-05-21 Thread Leandro Echevarría via USRP-users
Hey Nives, If it's of any help: on an X310, my utilization report for a design including a DMA_FIFO, both radio cores, two DDCs and two DUCs uses around 42% of the FPGA's Block RAM resources, and if I take out the DDCs and DUCs, the usage drops to around 34%. Regards, Lei On Mon, May 21, 2018 a

Re: [USRP-users] BRAM usage of the X300/X310 design

2018-05-21 Thread Nives Novković via USRP-users
Hi guys, Thank you very much for your answers. I managed to build the FPGA image on a new laptop, and I'm looking through utilization reports. :) I have another problem now, concerning flashing image to X310, but I'll open a new thread for that. Kind regards, Nives sub, 19. svi 2018. u 18:24 Rei

Re: [USRP-users] BRAM usage of the X300/X310 design

2018-05-19 Thread Reinhold Frederick William Hollender via USRP-users
There's a map option in ise that will give a very detailed listing if the resource usage of every block in your design hierarchy. I'm sure there's something similar for vivado. I can't remember the name of it, but I'm sure you can find it if you search around a little. Regards, William On Sat,

Re: [USRP-users] BRAM usage of the X300/X310 design

2018-05-19 Thread Neel Pandeya via USRP-users
We don't have a more-granular usage report for FPGA utilization. But you can experiment by removing blocks that you don't need, and seeing how many resources free up as a result. What is the error that you're seeing? Which version of Vivado are you using? Are you using the rfnoc-devel branch, or a

Re: [USRP-users] BRAM usage of the X300/X310 design

2018-04-23 Thread Nives Novković via USRP-users
Hi Martin, I saw that utilization report but as I can see it is not divided by blocks, it just says the complete usage of resources? I understand about not being able to provide the support for a completely stripped design, that is not my intention. I have also tried to build the project following

Re: [USRP-users] BRAM usage of the X300/X310 design

2018-04-19 Thread Martin Braun via USRP-users
On 04/19/2018 07:35 AM, Nives Novković via USRP-users wrote: > I can see by the official numbers that the default Ettus FPGA design on > X310 takes about 50% BRAM and on X300 about 90%. I would like to make my > own design for Ettus but use only ADC and Ethernet cores from the > default design. Doe

[USRP-users] BRAM usage of the X300/X310 design

2018-04-19 Thread Nives Novković via USRP-users
Hi everyone, I can see by the official numbers that the default Ettus FPGA design on X310 takes about 50% BRAM and on X300 about 90%. I would like to make my own design for Ettus but use only ADC and Ethernet cores from the default design. Does anybody know how much BRAM blocks would only those 2