Hi guys, Thank you very much for your answers. I managed to build the FPGA image on a new laptop, and I'm looking through utilization reports. :) I have another problem now, concerning flashing image to X310, but I'll open a new thread for that.
Kind regards, Nives sub, 19. svi 2018. u 18:24 Reinhold Frederick William Hollender < whollen...@gmail.com> napisao je: > There's a map option in ise that will give a very detailed listing if the > resource usage of every block in your design hierarchy. I'm sure there's > something similar for vivado. > > I can't remember the name of it, but I'm sure you can find it if you > search around a little. > > Regards, > William > > On Sat, May 19, 2018, 11:56 AM Neel Pandeya via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> We don't have a more-granular usage report for FPGA utilization. But you >> can experiment by removing blocks that you don't need, and seeing how many >> resources free up as a result. >> >> What is the error that you're seeing? Which version of Vivado are you >> using? Are you using the rfnoc-devel branch, or a tagged release such as >> 3.10.3.0 or 3.11.0.1? >> >> --Neel Pandeya >> >> >> >> >> On 23 April 2018 at 01:04, Nives Novković via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> Hi Martin, >>> >>> I saw that utilization report but as I can see it is not divided by >>> blocks, it just says the complete usage of resources? I understand about >>> not being able to provide the support for a completely stripped design, >>> that is not my intention. I have also tried to build the project following >>> the instructions but I got the error about design not satisfying timing >>> constraints. >>> >>> Kind regards, >>> Nives >>> >>> 2018-04-19 23:18 GMT+02:00 Martin Braun <martin.br...@ettus.com>: >>> >>>> On 04/19/2018 07:35 AM, Nives Novković via USRP-users wrote: >>>> > I can see by the official numbers that the default Ettus FPGA design >>>> on >>>> > X310 takes about 50% BRAM and on X300 about 90%. I would like to make >>>> my >>>> > own design for Ettus but use only ADC and Ethernet cores from the >>>> > default design. Does anybody know how much BRAM blocks would only >>>> those >>>> > 2 cores from the original design take up? Thank you in advance! >>>> >>>> Our current UHD images packages (which you get when you run >>>> uhd_images_downloader) include a utilization report. I'm assuming you >>>> mean you want to remove all RFNoC blocks except for the radio -- if you >>>> really want to remove *everything*, that would be an invasive change, >>>> for which we wouldn't be able to provide any support. >>>> >>>> -- M >>>> >>> >>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >
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