Thank you both, Marcus and Rob, for your responses! That clarifies
things—filter latency in the FPGA explains the dependency on sample rate. I
hadn’t fully considered that before. A signal change at the antenna takes time
to propagate, and with different filters engaged at varying sample rates,
I'm using timed commands to set the RX gain at a precise moment with the
following command:
set_command_time(md.time_spec + uhd::time_spec_t(0.02), 0);
However, I noticed that there is a delay between the specified time and the
actual time when the gain is applied. This delay is significantly l
Hello, \
\
I am currently facing an issue with ADC saturation on a USRP X310 equipped with
a UBX daughterboard. We are conducting measurements using an LTE signal and a
sinusoidal input signal, but it seems that the ADC is saturating, leading to a
loss of dynamic range in our measurements.
Test
After developing a C++ program and placing it in **`/uhd/host/utils`**, I
included it in **`CMakeLists.txt`**. However, when attempting to build the
program using **`make`** within **`/uhd/host/build`**, UHD is reporting that
it's unable to locate the C++ library I've used, specifically when inc
Hi,\
I am currently conducting frequency synchronization tests on two USRP X310
devices, each equipped with different daughterboards – the first with a UBX-40
v1 Dboard and the second with a WBX-v3 simple GDB Dboard. In my setup, I am
using an R&S SMF 100A generator to produce a sine wave spanni
