Re: [USRP-users] blocking one of channel in multi usrp

Hi Marcus, I have tried setting the tx_subdev "A:0 B:0 A:0 B:0" probably you mean only "A:0 B:0" since it produce another error saying input port already connected. I have tried another several benchmark configuration as follow: 1. ./benchmark_rate --tx_rate "1e6" --args "addr=192.168.40.2" --tx_su

Re: [USRP-users] blocking one of channel in multi usrp

Hi Marcus, Thank you for your respond, I just realize it seems somebody in the mail list has the same exact problem with me, but i check noone has answered to the problem. I have tried to run ./benchmark_rate --tx_rate "1e6" --args "addr0=192.168.40.2,addr1=192.168.50.2" --channels "0,2" --ref "ext

Re: [USRP-users] blocking one of channel in multi usrp

e time has a fixed > number of streams. What sampling rate are we talking about? Is continuity > for the other channels a concern? What is the time scale we're switching > channels on an off? > > Best regards, > Marcus > > > On 16 May 2018 13:02:01 GMT+02:00, harf

[USRP-users] Function Set_tx_antenna or set_rx_antenna

Hi All, I have question related to two function in UHD. There is a function to choose subdev (set_tx/rx_subdev_spec) and set antenna (set_tx/rx_antenna). What is the difference between these two function? If i choose for example subdev A:0, does it automatically select antenna in the RF A daughterb

[USRP-users] blocking one of channel in multi usrp

Hi all, Currently I am developing an application with multi usrp using two X310. My current configuration is using all 4 channel in usrp with all subdev enabled (A:0 B:0), both feed by an external clock. However I am curious if we have already issued stream command, is it possible to block one of t

Re: [USRP-users] Reference Clock PLL failed to lock external source during daisy chain

n that motherboard as you have specified, but the board doesnt > know if it is daisy chained or not, it just knows for that motherboard, use > the external port as its source... > > On May 14, 2018 at 6:58 PM harfan ryanu via USRP-users < > usrp-users@lists.ettus.com> wro

Re: [USRP-users] Reference Clock PLL failed to lock external source during daisy chain

implemented, at least > partially because it's not a wonderful idea in terms of added phase-noise, > and added clock and 1PPS skew between the two devices. > > > On May 14, 2018 at 4:28 AM harfan ryanu via USRP-users > wrote: > > Hi All, > I am building application

[USRP-users] Reference Clock PLL failed to lock external source during daisy chain

Hi All, I am building application with two USRP X310 configuration using daisy chain. When i try to synchronize both USRP using this : usrp.ptr->set_clock_source_out(true,0); usrp.ptr->set_time_source_out(true,0); usrp.ptr->set_clock_source("external",1); usrp.ptr->set_time_source("external",1);