e AXI wrapper instance in your block. AXI wrapper's s_axis_data_tready
signal essentially connects to a FIFO, so you should see it assert. Do you see
that?
Jonathon
On Fri, Aug 10, 2018, 5:52 PM TIMMEN Koen via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hello all,
Last
Hello all,
Last week I posted a question, on how I could confirm that a custom RFNoC
signal generator (piloted from a UHD API) functioned as intended. I received
the tip to probe my block using the Vivado ILA. A great idea, because I did not
know this existed (I am quite new in FPGA design) and
Brian,
I am not sure if I have stated my problem clearly. So I will reformulate: My
HDL module which I have verified using testbenches needs to be controlled from
the UHD API. However, I have trouble doing this. Following the two examples
available from the source directory I connected my block
De : Brian Padalino [mailto:bpadal...@gmail.com]
Envoyé : jeudi 2 août 2018 16:57
À : TIMMEN Koen
Cc : USRP-users@lists.ettus.com
Objet : Re: [USRP-users] UHD API
First, let me tell you that I've done this exact thing so it's very possible.
I also agree the current examples are poor in the UHD
Hello all,
I am working on a custom RFNoC based signal generator module on the X310 using
UBX daughterboards. I have created a custom signal generator NoC block, that
generates IQ samples based on register values and loaded this block together
with a DUC NoC block on a X310 RFNoC image. I wish
some future start time).
Regards,
Michael
On Wed, Jun 6, 2018 at 11:24 PM, TIMMEN Koen via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hello,
My block is a signal generator and each sample needs to be transmitted at an
accurately known instant. The samples themselves do not need t
ttle on the functionality you need pls, its not fully clear
enough to me to make a suggestion.
Are you trying to extract time from incoming samples or apply time to samples
you are processing?
-Ian
On Jun 5, 2018, at 7:36 AM, TIMMEN Koen via USRP-users
mailto:usrp-users@lists.ettus.com>>
Hello all,
Currently I'm working on a RFNoC block that requires a known time reference,
but I have trouble making this value available. Ideally I would like to have
the value available in a register designated to the block.
As I understand, a time reference is available through the CHDR, but..
Hello everyone,
Since a couple of months now, I've begun to work with FPGA development and have
been using RFNoC and the USRP X310 specifically. In other words, I'm just
starting to figure out this technology and still struggling with some of the
concepts used by the new USRP architecture and e
Hello,
First of all I would like to mention that I am not sure if this is the right
location to ask these type of questions. However, I tried to find answers to my
questions elsewhere but couldn't find a better suited location, so I hope I'm
not at the wrong address and causing too much clutter
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