[USRP-users] reinitializing N310 from MPM shell

2019-11-08 Thread Samuel Berhanu via USRP-users
Hello all, I was trying to reissue a daughterboard reset/reinitilzation for the N310 from MPM (I know at the uhd software stack there is force_reinit=1 argument that does this but can't use this right now). I tried to use the "init_dboards" command but was not sure what the argument that I need to

Re: [USRP-users] N310 generation of a project/bit file from Ettus design (HG version)

2019-10-24 Thread Samuel Berhanu via USRP-users
-0700 >> From: Robin Coxe >> To: Samuel Berhanu >> Cc: Ettus Mail List >> Subject: Re: [USRP-users] N310 generation of a project/bit file from >> Ettus design (HG version) >> Message-ID: >> < >> cakjydkls+-9dzyl04e8m8sqnvaxlk4nhkee3mgrmwu

Re: [USRP-users] N310 generation of a project/bit file from Ettus design (HG version)

2019-10-22 Thread Samuel Berhanu via USRP-users
o, I don't think the schematic is actually correct, for > the record. > > -Robin > > On Fri, Oct 18, 2019 at 8:33 AM Samuel Berhanu via USRP-users < > usrp-users@lists.ettus.com> wrote: > > > https://www.xilinx.com/support/answers/68238.html. This pretty much is

[USRP-users] Discrepancy between N310 MB Schematic and PS Pinout and other questions

2019-07-10 Thread Samuel Berhanu via USRP-users
The N310 design (i have tried both the HG and XG ) specify the following: UART0 on MIO pin 14:15, PJTAG on pin 10:13 UART1 on MIO pin 8:9 I2C0 on MIO pin 50:51 there is also GPIO pins on 46:49. All the above pins when looking at the MB schematic have different assignments. Namely, MIO 14:15 -> PS

[USRP-users] Tuning RF x310 daughterboard (SBX) from FPGA: Adjustment of Freq during runtime

2018-07-03 Thread Samuel Berhanu via USRP-users
Version of UHD i am using is 3.10.0 (pre_rfnoc) I have been attempting to change the RF frequency from the FPGA using SPI communication to do some frequency *hopping jumps in steps of 100 MHz after the first tuning call I am making from host. * What I am doing is: I create a custom "stream_live" s