other files in the compile.
Wade
On Fri, Nov 19, 2021 at 1:04 PM Rob Kossler mailto:rkoss...@nd.edu> > wrote:
Are you able to run the testbench for the provided "rfnoc-example" folder? I
notice that the gain testbench that is part of this example has the following
as the last
1:04 PM Rob Kossler mailto:rkoss...@nd.edu> > wrote:
Are you able to run the testbench for the provided "rfnoc-example" folder? I
notice that the gain testbench that is part of this example has the following
as the last statement. Perhaps this is needed?
`default_nettype wire
I'm trying to run the testbench for a new module I created (UHD4) and I'm
getting the following error:
INFO: [VRFC 10-2263] Analyzing Verilog file
"/home/nvd/uhd/fpga/usrp3/lib/control/gray2bin.v" into library
xil_defaultlib
INFO: [VRFC 10-311] analyzing module gray2bin
ERROR: [VRFC 10-1103]
Paolo,
Yes, it does sound like we are having slightly different issues here.
I am suppressing my output when data_ready from the AXI_Wrapper goes low. In
fact, even if I drop data (rather than queue it up) while data_ready is low,
I still get that 'D' message (even when making sure my sequence nu
y
suggestion
Thank you for your attention
Paolo
From: Rich, Michael via USRP-users
Sent: Monday, April 12, 2021 2:54 PM
To: usrp-users@lists.ettus.com
Subject: [USRP-users] AXI Stream Issue
I am having issues getting data out of a custom block NoC Block (on an X310
using UHD3.15) and I'
I am having issues getting data out of a custom block NoC Block (on an X310
using UHD3.15) and I'm not quite sure what would be causing what I'm seeing.
When everything starts up, it seems to work just fine for a bit, but then
output stops. Checking the data bus using an ILA, it appears as though
d