Hello,
I'm trying to bake an RFNoC image from the latest master, using Vivado
2018.3. However, I get DRC errors:
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin ce_clk with 1st
driver pin 'bus_clk_gen/CLK_OUT4' [/home/x/fpga/usrp3/top/x300/x300.v:284]
CRITICAL WARNING: [Synth 8-6859] mult
Hello,
we need to change the sample rate parameter of the DDC/DUC in the X310 in
runtime (under GNU Radio). This works in 3.9. However, with 3.14, the
flowgraph hangs upon trying to change the sample rate if using the
multi-USRP API, and we get "Timeout on channel 0" errors from gr-ettus and
flowg
Hello,
a question that keeps popping up on the list: is there a way to tag samples
within RFNoC such that it can be processed in GNU Radio?
In earlier discussions, the EOB bit was suggested for such purposes:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-June/020733.html
But I'm
Hello,
has anyone been successful reflashing the x3xx using xc3sprog or any other
command-line tool that is at least two orders of magnitude smaller than
Vivado Lab? :) When I'm trying to program the current (2017.4-generated)
images using xc3sprog, the usrp probe complains about unknown hardware
Hello,
I'm trying to hack together an RFNoC source block with two outputs, รก la
siggen but with more outputs obviously. Is it correct that I need two AXI
wrappers and two cvita_hdr_encoders, and I need to multiplex the outputs of
the AXI wrappers? If this is acceptable, what is the best way to imp
Phillipp,
you can ignore this error. It is a confirmed bug in the Xilinx toolchain,
supposedly has something to do with WebTalk. One would have to disable
WebTalk which is hard to suppress as it will be active every time when a
WebPACK license is being used. It is (?) fixed in the 2018.1 release.
Hello,
the clocking scheme has been recently changed, as of
https://github.com/EttusResearch/fpga/commit/89957c3f30d3e17ddd43622277cbec299b207805
But it seems that the rfnocmodtool Verilog template did not receive the
required changes, i.e., it leaves bus_clk and reset unconnected on the
axi_wrap
Hello,
a fresh pybombs (vanilla gnuradio-default on Ubuntu 16.04) install has
rendered my X310(+WBX-120/SBX) setups unusable. UHD insists that I update
the FPGA image (to compat number 34 which is I guess the Vivado
2017.4-generated one). After that, RX functionality gets crippled, I get
gr::log
