[USRP-users] X310 FPGA build problem

Dear All, I followed the build instruction for generation 3 on the website. All requirement and dependencies are fulfilled as well as Xilinx Vivado 2019.1. I would like to save the project in Vivado for future customization, therefore I ran "*make X310_HG GUI=1*". The makefile launch Vivado succes

[USRP-users] Different gain traces at RX interfaces

Hello All, My instrument (USRP X310) has 2 equivalent UBX-160 daughter boards. *| | | RX Dboard: A| | | ID: UBX-160 v2 (0x007e)| | | Serial: 31D5AC* * RX Dboard: B| | | ID: UBX-160 v2 (0x007e)| | | Serial: 31D5B02* I applied an equivalent external stimulus a

[USRP-users] USRP X310

Hello everybody, Does anybody know what is the maximum input power level of USRP-X310 in RX modus? National Instrument congratulation!! very bad documentation. Kind regards, Arash. -- Dipl.-Ing. Arash Jafari Phone: +43 650 844 3617 E-mail: arash.jafari.tele...@gmail.com _

[USRP-users] 12 bits I/Q samples

Hello Everybody, according to FPGA implementation of my board which a USRP-b200, the Least significant 4bits of I or Q samples are always 0 (0x???0), which in turn means the recorded sample as short complex 16 bits (sc16) cpu format should have four zero at LSB. But almost 10% of recorded samples