Hi,
the correct value for the --target parameter when building for x410 is “X410”:
```
$ rfnoc_image_builder -y x410_CG_400_rfnoc_image_core.yml --target X410
--vivado-path /opt/tools/Xilinx/Vivado/
```
However, the image core file already includes the default target value, this
means it is su
Hi, thanks for the reply. I’m using UHD 4.7. I ran the following and it worked
fine:\
\
$ source ../setupenv.sh --vivado-path=/opt/tools/Xilinx/Vivado/
Setting up a 64-bit FPGA build environment for the USRP-X4xx...
\- Vivado: Found (/opt/tools/Xilinx/Vivado//2021.1/bin)
Installed ve
Hi Martin
Thank your for your reply.
This is a software question, related to register peek and poke. For example,
if a register read (via ctrlport_endpoint_impl::peek32) is performed, is there
a chance that the software can block (or get stuck)?
Note: I am using UHD-4.7
kind regards,
Mari
Hey Marino,
not sure what you mean -- from software, or in general as a CHDR
transaction (e.g., from another RFNoC block)? Also, what do you want to
timeout: Is this for the case where there are too many commands in the
queue, and the backpressure is blocking (so you want to return without
doing t
