On 22/07/2024 18:39, cjohn...@serranosystems.com wrote:
Hi Marcus,
Thanks for the answer in 2).
What about 1) *FPGA Rx Buffer Size:*
*
What is the FPGA Rx buffer size on the X310?
I honestly don't know, and I'm not an FPGA guy, so diving into the FPGA
code likely won't enlighten eith
On 22/07/2024 18:39, cjohn...@serranosystems.com wrote:
Thank you Rob… I will explore this because I don’t want to deal with
DPDK. I read in other posts that it didn’t seem to make a difference.
It's certainly the case that at lower rates, DPDK won't make a
noticeable difference. At high sa
Hi Marcus,
Thanks for the answer in 2).
What about 1) **FPGA Rx Buffer Size:**
* What is the FPGA Rx buffer size on the X310?
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Thank you Rob… I will explore this because I don’t want to deal with DPDK. I
read in other posts that it didn’t seem to make a difference.
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Dear USRP Mailing List Members,
I would like to design a RF Front-End for the X440. I will limit the operations
of the receiver part to Nyquist Zone 1&2 by bandpass filters and converter rate
selection. However, I got confused in the transmitter side as I couldn't
determine which RF-DAC mode
(
Further to my last message:
After reading this:
https://lists.ettus.com/empathy/thread/FZYNEWJQYBKFJWC5LASSD5LOL6J765KU?hash=5JXCSAWOZJ6UEOSK3IPXZCIVS277B2SF#5JXCSAWOZJ6UEOSK3IPXZCIVS277B2SF
I tried this:
```
export UHD_FPGA_DIR=~/git/uhd/fpga/
```
```
export RFNOC_OOT=~/git/uhd/host/examples
Hi,
regarding FPGA Rx buffer, I am wondering if you can use the DRAM as a
buffer (e.g., host_tx => dram => duc => radio_tx). As far as I remember,
you can't use the DRAM as a FIFO if you are running 2 channels both at 200
MS/s. The DRAM FIFO bandwidth is insufficient. But, if your data rate is
le
Thanks for your reply. I resolved it once I updated Vivado with the patch from
Xilinx/AMD
https://support.xilinx.com/s/article/76780?language=en_US
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Hi All,
Is there an example on how to build the rfnoc-example in UHD 4.7 using the
rfnoc_image_builder utility?
Thanks,
Marino
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Hi,
Thanks for the answer in 2).
What about 1) **FPGA Rx Buffer Size:**
* What is the FPGA Rx buffer size on the X310?
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Hi,
I can add that we use switches quite a bit for the OAI CI testing, but
with fiber cabling (I think 25G and 100G). I could imagine that with
10G, you might run into issues because you cannot have that many
parallel streams (but that's more of a guess). Anyway, it seems to work
fine for us.
Rob
Hi,
yes, you can, but keep in mind that switches can be additional causes for
packet loss/reordering/other things, and potentially add latency. For 10
GbE you typically have a managed switch, and you should be able to
configure it (e.g., some switches have a configuration for maintaining
packet or
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