[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?

Hi sp, That sounds like a bad idea. How are you planning to synchronize access to that register? Generally, in almost *any* context, avoid global state. That makes things complicated and error prone; this is true for python as much as it is for C++, as much as it is for digital hardware desig

[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?

Hi, I tested your way but I have challenges with it. I described it in the below link. do you have any offer? Thanks very much https://lists.ettus.com/empathy/thread/A65LFSBUISOLPBGIRJWSJYBESRPMPEPC On Mon, Aug 1, 2022 at 1:47 PM Paolo Palana wrote: > For experimental purpose I did something li

[USRP-users] Re: X410 - FPGA unresponsive after several RFNoC Graph Creations

Hi Wade, thanks for the prompt reply. Indeed - UHD4.3 fixes this issue on X410. I tested it on my device and I was not running into this issue. Thanks, Max Maximilian Matthe Head of Engineering Lab maximilian.mat...@barkhauseninstitut.org Tel.: +49 173 4509667 _