Hi Kevin,
I assume the xml you're referring to is the component description so that
it can be recognized by Vivado IP integrator. In that case, you need to
create an instance of the IP in Vivado, which will create an XCI file for
it. You can then include that in the design similar to how other xci
Thanks very much. Jonathon and Yair. my problem is solved.
On Tue, Aug 30, 2022 at 5:38 AM Jonathon Pendlum
wrote:
> Hello,
>
> I suggest using LD_PRELOAD instead of UHD_MODULE_PATH, as UHD_MODULE_PATH
> will load all .so files in the directory.
>
> Jonathon
>
> On Mon, Aug 29, 2022 at 8:27 AM
Hi all,
I am using USRP E320. I was wondering if the RFNoC framework allows some
kind of bitstream protection/authentication like the bitstream encryption
option that offers vivado (
https://docs.xilinx.com/v/u/en-US/xapp1239-fpga-bitstream-encryption).
In that case, how can I load the encrypted b
Hi Everyone,
I’m a model-based firmware designer generating IP cores from Matlab and
Simulink.
I see from one of the Ettus tutorials that it is easy to include a core
defined by an “xci” file, but not the “xml” descriptions from Simulink.
(This was the rfnoc_block_gain exercise.)
The folder
