Please forgive me if this information is out there and I just happened
to miss it. I have an application where I won't have a good match
between one of the output TX ports on the USRP 2974 and the connected
load . What is the maximum permitted reflected power? Can I go all the
way to 20 dBm TX
Hi Bob,
Question 1:
With the x4 bitstream, the X410 puts a separate 10 GbE interface on each
lane of its QSFP28 port 0 (the QSFP port has four lanes). There are
breakout cables that go from one QSFP to four SFPs if you have cards with
SFP ports, or, if your card supports four 10 GbE ports on a sin
Sadly, I don't think there is one in the UHD repo. I don't know of anyone
who has written one.
Wade
On Wed, Jun 15, 2022 at 6:19 AM Florent Allard <
florent.all...@telecom-paris.fr> wrote:
> Hello,
>
> After having implemented into a RFNoC block the Xilinx IP LDPC Decoder and
> Encoder for 5G,
So I am on the x4_200 image and am wondering what the "correct" way to setup
the transport is.
I currently have a single qsfp28 connection on the x410 to a single 100 GbE
port on a mellanox card.
Question #1:
Looking at the description of the fpga image it describes the x4_200 as "4 x
10GbE",
Hello,
After having implemented into a RFNoC block the Xilinx IP LDPC Decoder and
Encoder for 5G, I’m trying to implement the Xilinx IP Polar Decoder/Encoder.
However, the Polar IP requires to be configured with an AXI4-Lite interface. I
know that RFNoC data planes are compliant with AXI-Stre
