[USRP-users] Re: How to add an ip core to rfnoc OOT block

Thanks Wade, then I'll check my clock domain crossings, guess I need a fifo between them. Kind Regards, Maria El mar., 14 jun. 2022 20:47, Wade Fife escribió: > Hi Maria, > > In the timing paths, take a look at the source clock and destination > clock. Are they the same clock? If not, then may

[USRP-users] Re: How to add an ip core to rfnoc OOT block

Hi Maria, In the timing paths, take a look at the source clock and destination clock. Are they the same clock? If not, then maybe you haven't handled the clock domain crossings correctly. If you lowered the clock frequency, the number of failing paths should go down, but if there are clock crossin

[USRP-users] Re: How to add an ip core to rfnoc OOT block

Hi again Wade, After making some synthesis with and without the clock wizard ip, I have observed that there is higher timing paths for those which use the ip rather than the ones which don't. I am lowing the clock for the design so I would expect the opposite behaviour. Alongside with the verilog

[USRP-users] Re: Is it possible that synthesis and generating bitstream in RFNOC blocks make faster??!!!

Thanks for the feedback! I will test them. On Tue, Jun 14, 2022 at 1:42 AM Wade Fife wrote: > Hi sp, > > It is possible to use incremental implementation using the checkpoints > generated by the build flow, but I've never tried it with USRPs. This is an > advanced Vivado feature so you would nee