Thanks, I edited the gain files now it works. All test was passed.
Vivado Simulator does not support tracing of System Verilog Dynamic Type
object.
TESTBENCH STARTED: chdr_crossbar_nxn: IP_OPTION = HDL_IP
OpenCL is not really a programming language, it is certainly not a hardware
synthesis language.
OpenCL is a set of extensions/libraries to a programming language (C, C++,
Python) that allow the programmer to distribute their calculations among
compute units in the system, where a compute unit i
The unmodified gain example should work, so I assume you modified it or are
trying your own version. I suggest you look at the example to see what you
did differently.
https://github.com/EttusResearch/uhddev/tree/master/host/examples/rfnoc-example/fpga/rfnoc_block_gain
The simulator is the tool d
On 2022-04-05 16:32, Caffrey, Michael Paul via USRP-users wrote:
Hi,
I apparently loaded a bad bistream onto my e320 (in case) and now it
seems bricked. I am trying to use the jtag programmer on vivado 2019.1
-> digilent onboard jtag programmer -> reprogram the fpga.
Unfortunately the stm32
Hi,
I apparently loaded a bad bistream onto my e320 (in case) and now it seems
bricked. I am trying to use the jtag programmer on vivado 2019.1 -> digilent
onboard jtag programmer -> reprogram the fpga. Unfortunately the stm32 turns
off the zynq as quickly as it comes up, is there a way to ove
On 4/1/22 08:40, Rob Kossler wrote:
Hi,
I am trying to copy some large files (~500MB) from the N310 to the host.
The transfer rate I get using scp or sshfs (mounting in either
direction) is about 12MB/s. Given that the interface itself can do
>100MB/s, I'm wondering if there is a faster metho
On 2022-04-05 15:00, Philip Balister wrote:
Does the Ettus image have iperf3 on it? I suppose I should remember
how it works and see if it has useful numbers.
That would help find the bottle neck.
Philip
It's almost certainly the encryption, given that there's a 3.5:1
improvement going from
Does the Ettus image have iperf3 on it? I suppose I should remember how
it works and see if it has useful numbers.
That would help find the bottle neck.
Philip
On 4/1/22 08:40, Rob Kossler wrote:
Hi,
I am trying to copy some large files (~500MB) from the N310 to the host.
The transfer rate I
Can you program the FPGA of either a E3X0 or B2X0 series using OpenCL,
SYCL or similar tooling?
It would be cool if you could program the onboard FPGA using C/C++ -
like tools and get real-time performance at high rates.
This might be wishful thinking but it looks like this is more and more
poss
