On 03/10/2021 06:15 PM, Rob Kossler via USRP-users wrote:
Hi Oliver,
I don't have any example code to provide (and I don't use gnuradio),
but I can address a couple of things:
- the first step is to get all four channels recognized (as you
indicated); perhaps using subdev spec "A:0 A:1 B:0 B:1"
Hi Oliver,
I don't have any example code to provide (and I don't use gnuradio), but I
can address a couple of things:
- the first step is to get all four channels recognized (as you indicated);
perhaps using subdev spec "A:0 A:1 B:0 B:1"
- synchronizing in time is definitely possible. From gnuradio
Hi,
I just modified one of my RFNoC blocks to use metadata for the first time.
The following remarks identify issues I encountered along the way and some
suggestions that would make things a bit easier.
- You can't use axis_data (with sideband signals) if you want access to
metadata. While I
A quick update ...
I added
#include
to my includes and the following code to UHD_SAFE_MAIN:
=
uhd::device3::sptr usrp3 = usrp->get_device3();
uhd::rfnoc::dma_fifo_block_ctrl::sptr dmafifo_block_ctrl =
usrp3->get_block_ctrl(
uhd::rfnoc::block_id_t(0,"D
You’ll need to familiarize yourself with this
https://files.ettus.com/manual/page_gpio_api.html
You should be able to tie a GPIO pin to the ATR state machine in the FPGA to
drive a GPIO output signal.
Sent from my iPhone
> On Mar 10, 2021, at 2:23 PM, SungWon Chung via USRP-users
> wrote:
Brian --
Thanks so much! I sprinkled my comments in below :
On Wed, Mar 10, 2021 at 1:42 PM Brian Padalino wrote:
> On Wed, Mar 10, 2021 at 12:39 PM Doug Blackburn wrote:
>
>> Brian,
>>
>> I've seen this using UHD-3.14 and UHD-3.15.LTS.
>>
>
> The DMA FIFO block default size is set here in t
Hello,
I'm working to use X300/X310 as a front-end of a custom built 60GHz mm-wave
transceiver, which needs a digital signal for its TX/RX switch to share a
horn antenna.
What do you think is the best solution?
Any methods are welcome as long as it's a robust solution. Your thoughts
will be much
On Wed, Mar 10, 2021 at 12:39 PM Doug Blackburn wrote:
> Brian,
>
> I've seen this using UHD-3.14 and UHD-3.15.LTS.
>
The DMA FIFO block default size is set here in the source code for
UHD-3.15.LTS:
https://github.com/EttusResearch/uhd/blob/UHD-3.15.LTS/host/lib/rfnoc/dma_fifo_block_ctrl_impl.
Hi
I am trying to set up an X310 with 2 TwinRX boards such that:
- each RF channel may be tuned to a different GNSS L-band frequency
- all four RF channels may be synchronised in time
- data streaming on all four channels at 100 MS/s (we are using dual 10G
Ethernet for this)
I'm pretty much a b
Brian,
I've seen this using UHD-3.14 and UHD-3.15.LTS.
I have performed some follow-on testing that raises more questions,
particularly about the usage of end_of_burst and start_of_burst. I talk
through my tests and observations below; the questions that these generated
are at the end ...
I tho
Hi Jules,
Thank you, I will try it and let you know as soon as possible.
By the way, I have checked the python generated using the UHD USRP SOURCE
block (instead of the RFNoC radio block) with AGC active and it generates
the set of AGC fine. So, as you said, it is fixed in gr-uhd but it might
sti
Maria,
So, if I understand correctly, I have to put there also something like
"self.ettus_rfnoc_rx_radio_0.set_rx_agc(enable,0)" isn't it?
Exactly! Take a look at [1] for the correct syntax.
[1]
https://github.com/EttusResearch/gr-ettus/blob/1038c4ce5135a2803b53554fc4971fe3de747d9a/include/e
Hi Julian,
Thanks for the quick answer.
I think you might be right about the possible bug turning on the AGC from
GRC. I have checked the flow graph generated and there's no set_rx_agc
enable option (I checked the c++ definition block where this option did
appear but I hadn't look at the python g
Maria,
I might not be the right person to answer this, as my experience with
UHD 4.0 is relatively limited at the moment.
However, I cant tell you that the AGC on B2x0 devices is controlled via
software (using set_rx_agc()). There is no need to directly modify the
state of any pins of the FP
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