Hi James,
The Siggen RFNoC block does not support timed commands.
Jonathon
On Wed, Jan 22, 2020 at 3:32 PM Xingjian Chen via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi,
> Is there a way to use timed command for E312 rfnoc siggen module for setup
> gain?
> I am trying something like be
Hello Group,
I am using the E312 to receive on both channels so I can use a dual antenna
system to determine the direction the received signal is coming from. I have
gotten the GPS, internal IMU working, and single channel RX working. The issue
is, when I try to receive on both channels simulta
Hi all,
I know there is a manual for this -
http://files.ettus.com/manual/page_identification.html#id_naming
Though I'm still having difficulties.
Firstly, can the eeprom of the device be read/changed from the device
itself?
I have ssh'd into the USRP, and get the following when attempting to
rea
Thank you Marcus, I was able to fix it by changing my network, as you
suggested.
Regards,
Saeid
On Wed, Jan 22, 2020 at 3:44 PM Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com> wrote:
> On 01/22/2020 03:37 PM, Saeid Hashemi via USRP-users wrote:
>
> Hello everyone,
>
> During the ins
On 01/22/2020 03:37 PM, Saeid Hashemi via USRP-users wrote:
Hello everyone,
During the installation of UHD, I get an unhandled exception when
downloading images. The resulting output is shown below. Any advice or
help would be greatly appreciated.
Thank you
Saeid
Reading package lists..
Hello everyone,
During the installation of UHD, I get an unhandled exception when
downloading images. The resulting output is shown below. Any advice or help
would be greatly appreciated.
Thank you
Saeid
Reading package lists... Done
Building dependency tree
Reading state information... Done
Hi,
Is there a way to use timed command for E312 rfnoc siggen module for setup gain?
I am trying something like below. Is this the right way? Thank you.
uhd::time_spec_t cmd_time = time_ref +
uhd::time_spec_t(i*256/28e6*10*2000*10);
ctrl_siggen_ch0->set_command_time(cmd_ti
Daniel,
The X310 has 1Gb of DRAM available to the FPGA. In the stock images, some
of this DRAM is used for FIFOs between RFNoC blocks. If you were to replace
these DRAM FIFOs with SRAM (i.e. compile the XGS image for X310), you
should theoretically be able to leverage all of the X310s DRAM in the
