Yeah, the driver tries to keep the DAC clock close to it’s max legal frequency
with the highest possible interpolation ratio from master_clock_rate.
That code doesn’t have any API access but I can show Sean how to hack it into
UHD if necessary.
> On Apr 10, 2019, at 10:57 PM, Julian Arnold via U
Sean,
if I remember correctly, the filter configuration (whether or not a filter is
bypassed) is determined by the ratio of DAC rate to master-clock rate (the
interpolation that needs to happen inside the ad9361) thus, you can only
somewhat,
indirectly, control it by changing the master-clock r
Thanks I will look into this. Right now, I have a modified FPGA HG image
for the x310 along with modified UHD and GNURadio source to handle some
additional inputs to the USRP. I'd like to try the new UHD, but I will
have to incorporate those changes into the source. I believe this will
necessita
Hi Mark,
We just merged DPDK support for the X3xx. You can try it out if you build
the current head of master. DPDK may help with 8 channels running at 100
MS/s each.
https://github.com/EttusResearch/uhd/commits/master
https://files.ettus.com/manual/page_dpdk.html
Regards,
Nate Temple
On Wed,
Okay thank you Marcus.
Mark
On Wed, Apr 10, 2019 at 3:09 PM Marcus D. Leech
wrote:
> On 04/10/2019 05:31 PM, Mark Gannet wrote:
>
> I've addressed the USRP as the following:
> USRP[0-3]: 192.168.4x.2, where x=0,1,2,3
>
> UHD 3.9.2
>
> You should probably upgrade to a newer UHD version. There w
On 04/10/2019 05:31 PM, Mark Gannet wrote:
I've addressed the USRP as the following:
USRP[0-3]: 192.168.4x.2, where x=0,1,2,3
UHD 3.9.2
You should probably upgrade to a newer UHD version. There were bugs in
that area, as I recall, that have since been fixed.
On Wed, Apr 10, 2019 at 1:47 PM
I've addressed the USRP as the following:
USRP[0-3]: 192.168.4x.2, where x=0,1,2,3
UHD 3.9.2
On Wed, Apr 10, 2019 at 1:47 PM Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com> wrote:
> On 04/10/2019 04:41 PM, Mark Gannet via USRP-users wrote:
> > I have 4 USRP x310s running at 12.5 MSa
On 04/10/2019 04:41 PM, Mark Gannet via USRP-users wrote:
I have 4 USRP x310s running at 12.5 MSa/sec on a quad 10GbE network
adapter (each USRP has it's own 10 GbE connection). I'm using the 16
bit short format.
I can operate one USRP at a time 100 MSa/sec with no overflows or
drops (200 MS
I have 4 USRP x310s running at 12.5 MSa/sec on a quad 10GbE network adapter
(each USRP has it's own 10 GbE connection). I'm using the 16 bit short
format.
I can operate one USRP at a time 100 MSa/sec with no overflows or drops
(200 MSa/sec total for one USRP). If I want to run all 4 USRP, I can
We'd like to bypass the Tx FIR filter and I'm wondering how to go about
this using the C++ api.
For the filter_base_info class there is the is_bypassed() function to read
the state, but no function to set it.
Should we be creating a new filter pointer with bypass set, and then using
it to overwrite
OK, I have a work-around to this for now. I needed to comment out the two
lines:
${CPPUNIT_INCLUDE_DIRS}
and
${CPPUNIT_LIBRARY_DIRS}
on lines 190 and 197 of gr-ettus/CMakeLists.txt.
I guess maybe a check needs to be done so that when it is determined that
CPPUINIT is getting ignored (like it
Trying to build a FPGA image with an OOT module is not going well. I first
built with standard blocks and that worked, so I know my setup is OK.
I then tried to build with my OOT module (and this used to work on an old
prefix), but now is erroring out because it can't find my OOT block. The
c
I am looping back to this. I thought I had things working, but I realized late
yesterday that my working prefix seemed to be based on a different
cross-compile environment (by working, I mean building. I still don't have my
e320 yet).
After I had it "working," I followed my steps again to ma
I believe I answered my own question. For anyone wondering -
RX subdev spec = A:AB B:0
Tx subdev spec = A:0 B:AB
Mike
On 04/10/2019 11:13 AM, Michael R. Freedman via USRP-users wrote:
Hello,
Can anyone tell me what the subdev spec should be when there is only
one BasicRX on one side an
Hello,
Can anyone tell me what the subdev spec should be when there is only one
BasicRX on one side and a
Basic TX is on the other side. I am only using the GPIO pins so don't
care at all about the analog section.
Thanks,
Mike
___
USRP-user
On 04/10/2019 01:49 AM, Koyel Das (Vehere) via USRP-users wrote:
Hi,
I am streaming data from USRP 2955R from 4 channels. Basic code is
rx_multisamples.cpp .
1.I want to scan frequencies that is change centre frequency on the
fly. So do I have to discard some packets after changing freque
Hi Leandro
Thank you for the answer, I will try to go that way and see what will be going
on.
Cherif
-Original Message-
From: Leandro Echevarría
Sent: dinsdag 9 april 2019 16:29
To: Cherif Diouf
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] PPS to custom RFNoC block
Hey C
Hi Kevin,
I got inverted spectrum (that means sign of I or Q is changed) when I
only set the frequency with use of timed commands. I described the
ranges in the original post. We did measurements in 100-500MHz band. You
can see phase difference between two TwinRXes here:
https://imgur.com/4C09MSf
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