Hi Marcus,
I am using an X310 model to implement loopback at 100MHz sampling rate. But
I can't use a 10G ethernet cable. But at the same time , i really get good
control on the rate of ADC/DAC irrespective of the data link speed ,
because i am not writing to or receiving from a file. Please help.
K
Yep
On Fri, Jul 21, 2017 at 11:54 AM, Jason Matusiak <
ja...@gardettoengineering.com> wrote:
> I need to re-setup my debug messages to check. To be clear, you are
> talking about the o_tdata (etc) up in my upper level
> noc_block_dataGenerator, right?
>
>
>
> On 07/21/2017 02:52 PM, Jonathon Pen
I need to re-setup my debug messages to check. To be clear, you are
talking about the o_tdata (etc) up in my upper level
noc_block_dataGenerator, right?
On 07/21/2017 02:52 PM, Jonathon Pendlum wrote:
Here is what should happen on the axi stream bus to the crossbar. You
should first see the
Hey Jason,
Here is what should happen on the axi stream bus to the crossbar. You
should first see the header on o_tdata with o_tvalid asserted. After a few
clock cycles, depending on how long arbitration takes, you should see
o_tready assert. Are you seeing that sequence?
Jonathon
On Fri, Jul 21
I am still struggling with my "output only" RFNoC block and can't seem
to figure out what silly thing I am doing wrong.
I am generating data by reading from a ROM and can see it happening by
monitoring the o_tdata (etc) lines coming from my lower module. If I
look in my noc_block_dataGenerator
The N210 had a nifty feature where we could redirect RX data packets to an
alternate IP. We could use that for multicast (I think). As far as I can tell
it is not a feature for x300 series. Any reason why? How hard would it be to
put it in?
___
Eugene Grayver, Ph.D.
Aer
Hi John,
the CC1120 is a cheap transceiver for GFSK. Unless you've driven it with
an oscillator that is way better than that of the B210, I don't really
see how your measurement could imply any clock drift on the B210's side?
Best regards,
Marcus
On 21.07.2017 10:41, john liu via USRP-users wr
Hi Karan,
what USRP model are we talking about?
Best regards,
Marcus
On 20.07.2017 07:51, Karan Suri via USRP-users wrote:
> Hello USRP Users
> I was able to develop an *FPGA based loop back which directs the raw
> ADC data to the DAC* . The TX transmits whatever it sees on the
> receive signa
Hi,Marcus,
We calculated this.
The B210 not only generate a GFSK signal,but also received the signal from
CC1120.The CC1120 and B210 both work in full duplex mode.
Hi qi,
Can you describe your test method?I am not clear for that.
best regards
John
On Fri, Jul 21, 2017 at 10:47 AM, Marcus D. Leec
