From: Thor Thayer
Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.
Signed-off-by: Thor Thayer
---
arch/arm/mach-socfpga/include/mach/firewall_s10.h | 7 +++
drivers/ddr/altera/sdram_s10.c| 14 ++
2 files changed, 21
On 11/18/19 1:27 AM, Marek Vasut wrote:
On 11/18/19 3:46 AM, Tan, Ley Foon wrote:
[...]
On 11/15/19 6:20 PM, Thor Thayer wrote:
Enable TCU access through the Stratix10 CCU so that the SMMU can
access the SDRAM.
[...]
Looks good to me. Ley, can you take a look?
Thanks!
Looks good to me
From: Thor Thayer
This patchset is rebased on top of [1] and adds SMMU
support for Stratix10 and fixes an ECC access issue
with Stratix10 and Agilex.
[1] [U-Boot,v8,00/19] Add Intel Agilex SoC support
https://patchwork.ozlabs.org/cover/1201373/
Thor Thayer (2):
arm: socfpga: stratix10
From: Thor Thayer
The ECC registers in the SDRAM HMC Adapter should always
be accessible (both when ECC is enabled and disabled).
Currently, the registers are accessible only when ECC is enabled.
The ECC Enabled bit is used to determine the status of
ECC by later OSes so always allow access
From: Thor Thayer
Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.
Signed-off-by: Thor Thayer
---
v2 Rebase patch on top of pending patchset
[PATCH v8 00/19] Add Intel Agilex SoC support
https://patchwork.ozlabs.org/cover/1201373/
---
arch/arm/mach
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