Hi Siva,
> -Ursprüngliche Nachricht-
> Von: Siva Durga Prasad Paladugu [mailto:siva...@xilinx.com]
> Gesendet: Montag, 11. Juni 2018 13:40
> An: ste...@herbrechtsmeier.net
> Cc: Herbrechtsmeier Dr.-Ing. , Stefan
> ; u-boot@lists.denx.de;
> Michal Simek ; mon...@monstr.eu
> Betreff: RE: [RF
Hi Michal,
> -Ursprüngliche Nachricht-
> Von: stefan.herbrechtsme...@weidmueller.com
>
> The old platform clock driver use a dynamic array which is filled at
> every boot with static clock tree information and unused clock rates.
> This needs much memory and complicates the strip down fo
Hi Michal,
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:michal.si...@xilinx.com]
> >
> Hi Stefan,
>
> On 6.2.2017 11:14, stefan.herbrechtsme...@weidmueller.com wrote:
> > Hi Michal,
> >
> >> -Ursprüngliche Nachricht-
> >> Von: stefan.herbrechtsme...@weidmueller.com
> >
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:michal.si...@xilinx.com]
>
> On 17.2.2017 10:21, Michal Simek wrote:
> > On 17.2.2017 08:33, stefan.herbrechtsme...@weidmueller.com wrote:
> >> Hi Michal,
> >>
> >>> -Ursprüngliche Nachricht-
> >>> Von: Michal Simek [mailto:mi
Hi,
> -Ursprüngliche Nachricht-
> Von: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
> Gesendet: Freitag, 25. November 2016 06:35
> An: Herbrechtsmeier, Stefan; u-boot@lists.denx.de
> Cc: Simon Glass; Masahiro Yamada; Stephen Warren; Heiko Schocher;
> Minkyu Kang; Wenyou Yang
> Betreff: Re
> Von: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
>
> On 11/22/2016 12:26 AM, Stefan Herbrechtsmeier wrote:
> > The zynq_sdhci controller driver use CONFIG_ZYNQ_SDHCI_MAX_FREQ as
> > base clock frequency but this clock is not fixed and depends on the
> > hardware configuration. Additionally the
> -Ursprüngliche Nachricht-
> Von: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
> Gesendet: Donnerstag, 1. Dezember 2016 07:43
> An: Herbrechtsmeier, Stefan; u-boot@lists.denx.de
> Cc: Simon Glass; Masahiro Yamada; Stephen Warren; Minkyu Kang; Wenyou
> Yang
> Betreff: Re: [PATCH v2 1/4] mm
From: Stefan Herbrechtsmeier
The sdhci controller assumes that the base clock frequency is fully
supported by the peripheral and doesn't support hardware limitations.
Distinguish between base clock of the host controller and maximal
supported peripheral clock frequency of the peripheral interfac
From: Stefan Herbrechtsmeier
The sdhci controller assumes that the base clock frequency is fully supported by
the peripheral and doesn't support hardware limitations. The Linux kernel
distinguishes between base clock (max_clk) of the host controller and maximum
frequency (f_max) of the card inter
From: Stefan Herbrechtsmeier
The index of the zynq serial driver is always zero and could be removed.
Signed-off-by: Stefan Herbrechtsmeier
Acked-by: Michal Simek
---
Changes in v3: None
Changes in v2:
- Remove unused index from get uart clock function
arch/arm/mach-zynq/clk.c
From: Stefan Herbrechtsmeier
The zynq_sdhci controller driver use CONFIG_ZYNQ_SDHCI_MAX_FREQ as base
clock frequency but this clock is not fixed and depends on the hardware
configuration. Additionally the value of CONFIG_ZYNQ_SDHCI_MAX_FREQ
doesn't match the real base clock frequency of SDIO_FREQ
From: Stefan Herbrechtsmeier
The maximum supported peripheral clock frequency of the zynq depends on
the IO routing. The MIO and EMIO support a maximum frequency of 50 MHz
respectively 25 MHz. Use the max-frequency value of the device tree to
determine the maximal supported peripheral clock frequ
Hi,
> -Ursprüngliche Nachricht-
> Von: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
>
> On 12/02/2016 10:24 PM, stefan.herbrechtsme...@weidmueller.de wrote:
> > From: Stefan Herbrechtsmeier
> >
> >
> > The sdhci controller assumes that the base clock frequency is fully
> > supported by
From: Stefan Herbrechtsmeier
The gem[0-1]_rclk_ctrl registers control the source of the rx clock,
control and data signals and configure via ps7_init function. Don't
overwrite the register with the default value.
Signed-off-by: Stefan Herbrechtsmeier
---
arch/arm/mach-zynq/slcr.c | 7 ---
From: Stefan Herbrechtsmeier
The old platform clock driver use a dynamic array which is filled at
every boot with static clock tree information and unused clock rates.
This needs much memory and complicates the strip down for the SPL.
The new clock framework driver contains the tree information
From: Stefan Herbrechtsmeier
If available use the clock framework to set the tx clock rate of the
zynq ethernet controller.
Signed-off-by: Stefan Herbrechtsmeier
---
arch/arm/include/asm/arch-zynqmp/sys_proto.h | 5 -
drivers/net/zynq_gem.c | 31
From: Stefan Herbrechtsmeier
If available use the clock framework to calculate the clock rate of the
zynq timer.
Signed-off-by: Stefan Herbrechtsmeier
---
arch/arm/mach-zynq/timer.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/mach-zynq/timer.c b/arc
From: Stefan Herbrechtsmeier
The clock names are static and correspond to the clock id. Separate
them from the dynamic filled clock array.
Signed-off-by: Stefan Herbrechtsmeier
---
arch/arm/mach-zynq/clk.c | 121 +++
1 file changed, 60 insertions(+)
From: Stefan Herbrechtsmeier
The zynq_clk_get_name function is only used once inside the clock
driver. Replace the function call with the one-line code.
Signed-off-by: Stefan Herbrechtsmeier
---
arch/arm/mach-zynq/clk.c | 12 +---
arch/arm/mach-zynq/include/mach/clk.h |
From: Stefan Herbrechtsmeier
Move the zynq to clock framework and remove unused functions as well as
the CONFIG_ZYNQ_PS_CLK_FREQ configuration.
Signed-off-by: Stefan Herbrechtsmeier
---
arch/arm/Kconfig| 2 +
arch/arm/dts/zynq-7000.dtsi | 2 +
a
From: Stefan Herbrechtsmeier
Add support for the optional ethernet emio clock source to the zynq
clock framework driver.
Signed-off-by: Stefan Herbrechtsmeier
---
drivers/clk/clk_zynq.c | 33 +++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/dri
From: Stefan Herbrechtsmeier
Add a clock framework driver for the zynq platform. The driver is based
on the platform zynq clock driver but reworked to use static functions
instead of run-time generated objects even for unused clocks.
Additionally the CONFIG_ZYNQ_PS_CLK_FREQ is replaced by the
ps-
Hi Michael
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:michal.si...@xilinx.com]
> Gesendet: Dienstag, 6. Dezember 2016 13:59
> An: Jaehoon Chung; Herbrechtsmeier, Stefan; u-boot@lists.denx.de
> Cc: Michal Simek; Simon Glass; Albert Aribaud; Michal Simek; Stephen
> Warren
> Betr
Hi Michal,
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:michal.si...@xilinx.com]
> Gesendet: Dienstag, 10. Januar 2017 14:30
> An: Herbrechtsmeier, Stefan; michal.si...@xilinx.com;
> jh80.ch...@samsung.com; u-boot@lists.denx.de
> Cc: s...@chromium.org; mon...@monstr.eu; swar...@
Hi Michal,
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:mon...@monstr.eu]
> Gesendet: Dienstag, 10. Januar 2017 14:53
> An: Herbrechtsmeier, Stefan; u-boot@lists.denx.de
> Cc: Herbrechtsmeier, Stefan; Michal Simek; Jagan Teki; Albert Aribaud;
> Joe Hershberger; Mike Looijmans
>
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:mon...@monstr.eu]
> Gesendet: Dienstag, 10. Januar 2017 14:59
> An: Herbrechtsmeier, Stefan; u-boot@lists.denx.de
> Cc: Herbrechtsmeier, Stefan; Albert Aribaud; Michal Simek; Joe
> Hershberger
> Betreff: Re: [PATCH 2/8] net: zynq: Add
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:mon...@monstr.eu]
> Gesendet: Dienstag, 10. Januar 2017 15:10
> An: Herbrechtsmeier, Stefan; u-boot@lists.denx.de
> Cc: Albert Aribaud; Herbrechtsmeier, Stefan
> Betreff: Re: [PATCH 3/8] zynq: Add clk framework support to zynq timer
>
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:mon...@monstr.eu]
> Gesendet: Dienstag, 10. Januar 2017 15:57
>
> +Soren
>
> On 4.1.2017 13:27, stefan.herbrechtsme...@weidmueller.com wrote:
> > From: Stefan Herbrechtsmeier
> >
> > Add a clock framework driver for the zynq platfor
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:mon...@monstr.eu]
> Gesendet: Dienstag, 10. Januar 2017 16:23
>
> On 10.1.2017 15:46, stefan.herbrechtsme...@weidmueller.com wrote:
> >> -Ursprüngliche Nachricht-
> >> Von: Michal Simek [mailto:mon...@monstr.eu]
> >> Gesendet:
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:michal.si...@xilinx.com]
> Gesendet: Dienstag, 10. Januar 2017 16:39
>
> On 10.1.2017 15:05, stefan.herbrechtsme...@weidmueller.com wrote:
> > Hi Michal,
> >
> >> -Ursprüngliche Nachricht-
> >> Von: Michal Simek [mailto:michal
> -Ursprüngliche Nachricht-
> Von: Michal Simek [mailto:michal.si...@xilinx.com]
> Gesendet: Mittwoch, 11. Januar 2017 09:22
>
> On 11.1.2017 08:30, stefan.herbrechtsme...@weidmueller.com wrote:
> >> -Ursprüngliche Nachricht-
> >> Von: Michal Simek [mailto:mon...@monstr.eu]
> >> Ge
From: Stefan Herbrechtsmeier
The sdhci controller assumes that the base clock frequency is fully supported by
the peripheral and doesn't support hardware limitations. The Linux kernel
distinguishes between base clock (max_clk) of the host controller and maximum
frequency (f_max) of the card inter
From: Stefan Herbrechtsmeier
The sdhci controller assumes that the base clock frequency is fully
supported by the peripheral and doesn't support hardware limitations.
Distinguish between base clock of the host controller and maximal
supported peripheral clock frequency of the peripheral interfac
From: Stefan Herbrechtsmeier
If available use the clock framework to set the tx clock rate of the
zynq ethernet controller.
Signed-off-by: Stefan Herbrechtsmeier
---
Changes in v2:
- Rebase
arch/arm/include/asm/arch-zynqmp/sys_proto.h | 7 ---
drivers/net/zynq_gem.c
From: Stefan Herbrechtsmeier
The gem[0-1]_rclk_ctrl registers control the source of the rx clock,
control and data signals and configure via ps7_init function. Don't
overwrite the register with the default value.
Signed-off-by: Stefan Herbrechtsmeier
---
Changes in v2: None
arch/arm/mach-zyn
From: Stefan Herbrechtsmeier
The zynq_clk_get_name function is only used once inside the clock
driver. Replace the function call with the one-line code.
Signed-off-by: Stefan Herbrechtsmeier
Reviewed-by: Michal Simek
---
Changes in v2: None
arch/arm/mach-zynq/clk.c | 12 +--
From: Stefan Herbrechtsmeier
If available use the clock framework to calculate the clock rate of the
zynq timer.
Signed-off-by: Stefan Herbrechtsmeier
---
Changes in v2: None
arch/arm/mach-zynq/timer.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/ma
From: Stefan Herbrechtsmeier
The clock names are static and correspond to the clock id. Separate
them from the dynamic filled clock array.
Signed-off-by: Stefan Herbrechtsmeier
Reviewed-by: Michal Simek
---
Changes in v2: None
arch/arm/mach-zynq/clk.c | 121 +++--
From: Stefan Herbrechtsmeier
Add a clock framework driver for the zynq platform. The driver is based
on the platform zynq clock driver but reworked to use static functions
instead of run-time generated objects even for unused clocks.
Additionally the CONFIG_ZYNQ_PS_CLK_FREQ is replaced by the
ps-
From: Stefan Herbrechtsmeier
Add support for the optional ethernet emio clock source to the zynq
clock framework driver.
Signed-off-by: Stefan Herbrechtsmeier
---
Changes in v2:
- Return a error and print a debug message if a gem emio rx clock
source is unknown
- Correct the checks for vali
From: Stefan Herbrechtsmeier
Move the zynq to clock framework and remove unused functions as well as
the CONFIG_ZYNQ_PS_CLK_FREQ configuration.
Signed-off-by: Stefan Herbrechtsmeier
---
Changes in v2:
- Add support for unknown clock rate to soc_clk_dump()
arch/arm/Kconfig
From: Stefan Herbrechtsmeier
The zynq_sdhci controller driver use CONFIG_ZYNQ_SDHCI_MAX_FREQ as base
clock frequency but this clock is not fixed and depends on the hardware
configuration. Additionally the value of CONFIG_ZYNQ_SDHCI_MAX_FREQ
doesn't match the real base clock frequency of SDIO_FREQ
From: Stefan Herbrechtsmeier
The maximum supported peripheral clock frequency of the zynq depends on
the IO routing. The MIO and EMIO support a maximum frequency of 50 MHz
respectively 25 MHz. Use the max-frequency value of the device tree to
determine the maximal supported peripheral clock frequ
From: Stefan Herbrechtsmeier
The old platform clock driver use a dynamic array which is filled at
every boot with static clock tree information and unused clock rates.
This needs much memory and complicates the strip down for the SPL.
The new clock framework driver contains the tree information
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