e tried to keep things such that the U-Boot and Linux
versions can be compared and kept in sync.
[1] -
https://lore.kernel.org/all/20221108122254.1185-2-ibrahim.ti...@analog.com/
Chris Packham (2):
include: kernel.h: port find_closest() from Linux
drivers: rtc: add max313xx series rtc driver
The find_closest() macro can be used to find an element in a sorted
array that is closest to an input value.
Signed-off-by: Chris Packham
---
include/linux/kernel.h | 24
1 file changed, 24 insertions(+)
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
set is added
Signed-off-by: Chris Packham
---
drivers/rtc/Kconfig| 8 +
drivers/rtc/Makefile | 1 +
drivers/rtc/max313xx.c | 442 +
3 files changed, 451 insertions(+)
create mode 100644 drivers/rtc/max313xx.c
diff --git a/drivers/rtc/Kconfi
from Simon
- Enable in sandbox for compile testing
- Note feature omissions in Kconfig
- Incorporate review comments from Simon
- Collect r-by from Simon
Chris Packham (2):
include: kernel.h: port find_closest() from Linux
drivers: rtc: add max313xx series rtc driver
configs/sandbox_defconfig | 1
The find_closest() macro can be used to find an element in a sorted
array that is closest to an input value. Bring in this macro from
Linux v6.3-rc1-2-g8ca09d5fa354.
Signed-off-by: Chris Packham
Reviewed-by: Simon Glass
---
Changes in v2:
- Add note on which Linux version this came from
set is added
Signed-off-by: Chris Packham
Reviewed-by: Simon Glass
---
Changes in v2:
- Enable in sandbox for compile testing
- Note feature omissions in Kconfig
- Incorporate review comments from Simon
- Collect r-by from Simon
configs/sandbox_defconfig | 1 +
drivers/rtc/Kconfig |
Hi,
I'm looking to upstream support for a new board with the Marvell AC5X
SoC and some NAND driver changes to support the SoC/board. I've got
things working when chain loading vendor based u-boot -> upstream
u-boot but when I boot directly the NAND controller reports
"pxa3xx-nand nand-controller@8
Answering my own question (I think)
On Mon, Jul 3, 2023 at 12:10 PM Chris Packham wrote:
>
> Hi,
>
> I'm looking to upstream support for a new board with the Marvell AC5X
> SoC and some NAND driver changes to support the SoC/board. I've got
> things working when chain
ince I was touching the NAND
driver.
Chris Packham (6):
arm: mvebu: ac5: Add nand-controller node
arm: mvebu: ac5: Define mvebu_get_nand_clock()
mtd: nand: pxa3xx: Add support for the Marvell AC5 SoC
mtd: nand: pxa3xx: Enable devbus/nand arbiter on Armada 8K
arm: mvebu: Add Allied Telesis x24
The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping
or gating require so just add a mvebu_get_nand_clock() that
returns this value.
Signed-off-by: Chris Packham
---
arch/arm/mach-mvebu/alleycat5/soc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-
The AC5/AC5X SoC has a NAND flash controller. Add this to the
SoC device tree.
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx25xx.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/ac5-98dx25xx.dtsi b/arch/arm/dts/ac5-98dx25xx.dtsi
index 3c68355f323a
The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as
the NFC used on other Marvell SoCs. It does have the additional
restriction of only supporting SDR timing modes up to 3.
Signed-off-by: Chris Packham
---
drivers/mtd/nand/raw/pxa3xx_nand.c | 17 ++---
1 file changed
unless the NfArbiterEn bit is set. Setting the bit enables
arbitration between the Device Bus and the NAND flash.
Since there is no obvious downside in enabling this for designs that
don't require arbitration, we always enable it.
Signed-off-by: Chris Packham
---
drivers/mtd/nand/raw/pxa3xx_n
The x240 and SE240 are a series of L2+ switches from Allied Telesis.
There are a number of them in the range but as far as U-Boot is
concerned all the CPU block components are the same so there's only one
board defined.
Signed-off-by: Chris Packham
---
arch/arm/dts/Mak
The sar-reg0 alias was left over from an earlier iteration of the
patches adding support for this board. Remove the unused alias.
Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board")
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx35xx-rd.dts | 1 -
1 file changed, 1 deletio
On Mon, Jul 3, 2023 at 3:39 PM Chris Packham wrote:
>
> The x240 and SE240 are a series of L2+ switches from Allied Telesis.
> There are a number of them in the range but as far as U-Boot is
> concerned all the CPU block components are the same so there's only one
> board def
ince I was touching the NAND
driver.
Chris Packham (6):
arm: mvebu: ac5: Add nand-controller node
arm: mvebu: ac5: Define mvebu_get_nand_clock()
mtd: nand: pxa3xx: Add support for the Marvell AC5 SoC
mtd: nand: pxa3xx: Enable devbus/nand arbiter on Armada 8K
arm: mvebu: Add Allied Telesis x24
The AC5/AC5X SoC has a NAND flash controller. Add this to the
SoC device tree.
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx25xx.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/ac5-98dx25xx.dtsi b/arch/arm/dts/ac5-98dx25xx.dtsi
index 3c68355f323a
The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping
or gating require so just add a mvebu_get_nand_clock() that
returns this value.
Signed-off-by: Chris Packham
---
arch/arm/mach-mvebu/alleycat5/soc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-
The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as
the NFC used on other Marvell SoCs. It does have the additional
restriction of only supporting SDR timing modes up to 3.
Signed-off-by: Chris Packham
---
drivers/mtd/nand/raw/pxa3xx_nand.c | 17 ++---
1 file changed
unless the NfArbiterEn bit is set. Setting the bit enables
arbitration between the Device Bus and the NAND flash.
Since there is no obvious downside in enabling this for designs that
don't require arbitration, we always enable it.
Signed-off-by: Chris Packham
---
drivers/mtd/nand/raw/pxa3xx_n
The x240 and SE240 are a series of L2+ switches from Allied Telesis.
There are a number of them in the range but as far as U-Boot is
concerned all the CPU block components are the same so there's only one
board defined.
Signed-off-by: Chris Packham
---
Notes:
Changes in v2:
-
The sar-reg0 alias was left over from an earlier iteration of the
patches adding support for this board. Remove the unused alias.
Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board")
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx35xx-rd.dts | 1 -
1 file changed, 1 deletio
In some designs the MAX313xx RTC may need calibration to cope with
oscillator inaccuracies. Provide read8/write8 ops so that the registers
can be accessed. Because the driver covers a range of MAX313xx variants
no attempt is made to ensure the register is valid.
Signed-off-by: Chris Packham
gpio_request_list_by_name() returns the number of gpios requested.
Notably it swallows the underlying -ENOENT when the "gpios" property
does not exist.
Update the i2c-gpio driver to check for ret == 0 before trying the new
sda-gpios/scl-gpios properties.
Signed-off-by: Chr
controller and avoids
triggering the Errata.
Signed-off-by: Chris Packham
---
This is dependent on a bug-fix for the i2c-gpio driver I just sent
out[1] (sorry I should have sent them as a series but I thought this
would take me longer to test than it did).
[1] -
https://lore.kernel.org/u-boot
Hi Me,
On Thu, Jul 20, 2023 at 3:03 PM Chris Packham wrote:
>
> There is an Errata with the built-in I2C controller where various I2C
> hardware errors cause a complete lockup of the CPU (which eventually
> results in an watchdog reset).
>
> Put the I2C MPP pins into GPIO mo
Hi Marc, Paul,
On Sat, Mar 18, 2023 at 5:23 AM Ying-Chun Liu (PaulLiu)
wrote:
>
> From: Marc Zyngier
>
> Some recent arm64 cores have a facility that allows the page
> table walker to track the dirty state of a page. This makes it
> really efficient to perform CMOs by VA as we only need to look
or is because the physical address of the RAM on the AC5X SoC is
above the 32GiB boundary. As we don't need SMBIOS or EFI this can be
safely disabled.
Signed-off-by: Chris Packham
---
This probably should have been part of the series I sent as
https://lore.kernel.org/u-boot/20231003035800
On Sat, 14 Oct 2023, 11:04 am Marc Zyngier, wrote:
> On 2023-10-13 03:40, Chris Packham wrote:
> > Hi Marc, Paul,
> >
> > On Sat, Mar 18, 2023 at 5:23 AM Ying-Chun Liu (PaulLiu)
> > wrote:
> >>
> >> From: Marc Zyngier
> >>
> >&g
On Sun, Oct 15, 2023 at 10:29 AM Chris Packham wrote:
>
>
>
> On Sat, 14 Oct 2023, 11:04 am Marc Zyngier, wrote:
>>
>> On 2023-10-13 03:40, Chris Packham wrote:
>> > Hi Marc, Paul,
>> >
>> > On Sat, Mar 18, 2023 at 5:23 AM Ying-Chun Liu (P
On Tue, Oct 17, 2023 at 12:21 AM Marc Zyngier wrote:
>
> On Mon, 16 Oct 2023 02:42:08 +0100,
> Chris Packham wrote:
> >
> > On Sun, Oct 15, 2023 at 10:29 AM Chris Packham
> > wrote:
> > >
> > >
> > >
> > > On Sat, 14 Oct 2023, 1
simple fixed page table size rather than
trying to duplicate the more complicated logic to optimise the table
size.
Signed-off-by: Chris Packham
---
arch/arm/mach-mvebu/alleycat5/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c
b/arch/arm/ma
On Fri, 20 Oct 2023, 7:18 pm Stefan Roese, wrote:
> Hi Chris,
>
> On 10/18/23 22:53, Chris Packham wrote:
> > Since commit 6cdf6b7a340d ("arm64: Use FEAT_HAFDBS to track dirty pages
> > when available") the default get_page_table_size() sets some flags for
>
On Sat, 21 Oct 2023, 2:04 am Marc Zyngier, wrote:
> On 2023-10-18 21:53, Chris Packham wrote:
> > Since commit 6cdf6b7a340d ("arm64: Use FEAT_HAFDBS to track dirty pages
> > when available") the default get_page_table_size() sets some flags for
> > more efficie
As discussed this series reverts the HAFDBS changes that caused an issue
on AC5/AC5X. I think there are some improvements that can be made to the
initial memory map for the AC5/AC5X but so far nothing I've found makes
it compatible with the HAFDBS changes.
Chris Packham (3):
Revert &
this series is the best course of action.
Signed-off-by: Chris Packham
---
arch/arm/cpu/armv8/cache_v8.c| 6 +-
arch/arm/include/asm/armv8/mmu.h | 10 ++
2 files changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
this series is the best course of action.
Signed-off-by: Chris Packham
---
arch/arm/cpu/armv8/cache_v8.c | 14 --
arch/arm/include/asm/global_data.h | 1 -
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
this series is the best course of action.
Signed-off-by: Chris Packham
---
arch/arm/cpu/armv8/cache_v8.c | 16 +---
arch/arm/include/asm/armv8/mmu.h | 14 --
arch/arm/include/asm/global_data.h | 1 -
3 files changed, 5 insertions(+), 26 deletions(-)
diff --git a
-off-by: Chris Packham
---
arch/arm/mach-mvebu/alleycat5/cpu.c | 66 ++---
1 file changed, 51 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c
b/arch/arm/mach-mvebu/alleycat5/cpu.c
index 8204d9627515..0f72ae1709be 100644
--- a/arch/arm/mach
Hi Tom,
On Fri, 27 Oct 2023, 1:54 pm Tom Rini, wrote:
> On Fri, Oct 27, 2023 at 01:44:11PM +1300, Chris Packham wrote:
>
> > The ATF implementation for AC5/AC5X ends up with bl31 living in some
> > internal SRAM. This is in the middle of the large MMIO region that we
> >
The CN9130-DB uses the SPI1 interface but had the pinctrl node labelled
as "cp0_spi0_pins". Use the label "cp0_spi1_pins" and update the node
name to "cp0-spi-pins-1" to avoid confusion with the pinctrl options for
SPI0.
Signed-off-by: Chris Packham
---
arch/arm/d
The cn9130.dtsi defines a pinctrl node for SPI1 (until recently it was
mislabeled as spi0). Use this instead of having a duplicate definition
with a different label.
Signed-off-by: Chris Packham
---
arch/arm/dts/cn9130-crb.dtsi | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham
---
drivers/net/Kconfig | 2 +-
drivers/net/mvneta.c | 66
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham
---
drivers/pinctrl/mvebu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 574fb4dfb0..7c51d138c8 100644
--- a/drivers
Add a new UCLASS_SAR, the generic SAR code and an Alleycat5 driver. This
has been adapted from the Marvell SDK but only the AC5 driver has been
brought through (other drivers exist for the ap806, ap807 and cp110 IP
blocks).
Signed-off-by: Chris Packham
---
drivers/misc/Kconfig
780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/ac5-98dx35xx-rd.dts | 155
t.
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx25xx.dtsi | 292 +++
arch/arm/dts/ac5-98dx35xx.dtsi | 17 ++
arch/arm/mach-mvebu/Kconfig | 5 +
arch/arm/mach-mvebu/Makefile | 1 +
arch/arm/mach-mvebu/alleycat5/Makefi
attempt to patch it (the images will work over UART
boot as-is). This is done by checking for a specific magic value
("TIMH") in the first 32bits of the image.
Signed-off-by: Chris Packham
---
It might be possible to make the check more robust by validating more of
the image. There is a check
ods (2
different transfer with 2 different protocols).
I do wonder if the boot seqence and xmodem stuff could be abstracted out to
something that could be reused by other tools.
I the short term at least I'll drop this out of the series.
>
> On Friday 16 September 2022 16:54:23 Chris Pack
l
land in Linux 6.0 although there are still some differences
Chris Packham (7):
net: mvneta: Add support for AlleyCat5
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
pinctrl: mvebu: Add AlleyCat5 support
misc: mvebu: Add sample at reset driver
arm: mvebu: Support for 98DX25xx/98D
On Fri, 16 Sep 2022, 10:58 PM Pali Rohár, wrote:
> On Friday 16 September 2022 16:54:22 Chris Packham wrote:
> > +&spi0 {
> > + status = "okay";
> > +
> > + spiflash0: flash@0 {
> > + compatible = "jedec,spi-n
Hi Pali,
On Sat, Sep 17, 2022 at 12:37 AM Pali Rohár wrote:
>
> On Friday 16 September 2022 22:34:52 Chris Packham wrote:
> > I do wonder if the boot seqence and xmodem stuff could be abstracted out to
> > something that could be reused by other tools.
>
> In the past
On Mon, Sep 19, 2022 at 11:03 AM Pali Rohár wrote:
>
> On Monday 19 September 2022 10:57:10 Chris Packham wrote:
> > Having looked more into mox-imager (and WtpDownloader) I've realised
> > that the AlleyCat5 uses something called "TIM" but it's different to
at will
land in Linux 6.0 although there are still some differences
Changes in v2:
- Use distro boot by default
- remove unnecessary SPI-NOR partitions
Chris Packham (6):
net: mvneta: Add support for AlleyCat5
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
pinctrl: mvebu: Add AlleyCat5
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham
---
(no changes since v1)
drivers/net/Kconfig | 2 +-
drivers/net/mvneta.c | 66
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham
---
(no changes since v1)
drivers/pinctrl/mvebu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 574fb4dfb0
Add a new UCLASS_SAR, the generic SAR code and an Alleycat5 driver. This
has been adapted from the Marvell SDK but only the AC5 driver has been
brought through (other drivers exist for the ap806, ap807 and cp110 IP
blocks).
Signed-off-by: Chris Packham
---
(no changes since v1)
drivers/misc
t.
Signed-off-by: Chris Packham
---
(no changes since v1)
arch/arm/dts/ac5-98dx25xx.dtsi | 292 +++
arch/arm/dts/ac5-98dx35xx.dtsi | 17 ++
arch/arm/mach-mvebu/Kconfig | 5 +
arch/arm/mach-mvebu/Makefile | 1 +
arch/arm/
780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham
---
Changes in v2:
- Use distro boot by default
- remove unnecessary SPI-NOR partitions
arch/arm/dts
On Tue, Sep 20, 2022 at 9:17 PM Stefan Roese wrote:
>
> On 20.09.22 10:31, Chris Packham wrote:
> > Add support for the AlleyCat5 SoC. This lacks the mbus from the other
> > users of the mvneta.c driver so a new compatible string is needed to
> > allow for a differ
On Tue, Sep 20, 2022 at 10:48 PM Pali Rohár wrote:
>
> On Tuesday 20 September 2022 20:31:48 Chris Packham wrote:
> > diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
> > index d2c42c4396..07919d6d35 100644
> > --- a/drivers/net/mvneta.c
> > +++ b/drivers/n
On Tue, Sep 20, 2022 at 9:22 PM Pali Rohár wrote:
>
> On Tuesday 20 September 2022 20:31:52 Chris Packham wrote:
> > Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
> > an integrated CPU (referred to as the CnM block in Marvell's
> > documentat
boot by default
- remove unnecessary SPI-NOR partitions
Chris Packham (6):
net: mvneta: Add support for AlleyCat5
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
pinctrl: mvebu: Add AlleyCat5 support
misc: mvebu: Add sample at reset driver
arm: mvebu: Support for 98DX25xx/98DX35xx SoC
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
Changes in v3:
- Remove unnecessary changes to RX
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham
---
(no changes since v1)
drivers/pinctrl/mvebu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 574fb4dfb0
Add a new UCLASS_SAR, the generic SAR code and an Alleycat5 driver. This
has been adapted from the Marvell SDK but only the AC5 driver has been
brought through (other drivers exist for the ap806, ap807 and cp110 IP
blocks).
Signed-off-by: Chris Packham
---
Changes in v3:
- None. Note some
t.
Signed-off-by: Chris Packham
---
Changes in v3:
- Remove unnecessary dma-ranges property from ethernet nodes (mvneta now
correctly parses the property from the parent node).
- Keep soc_print_clock_info and soc_print_device_info local to
alleycat5.
arch/arm/dts/ac5-98dx25xx.dtsi
780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham
---
Changes in v3:
- Remove MMC and UBIFS distroboot options (MMC driver is not currently
functional, NAND
On Wed, Sep 21, 2022 at 5:58 PM Stefan Roese wrote:
>
> On 21.09.22 06:59, Chris Packham wrote:
> > Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
> > an integrated CPU (referred to as the CnM block in Marvell's
> > documentation). These have
On Wed, Sep 21, 2022 at 5:58 PM Stefan Roese wrote:
>
> On 21.09.22 06:59, Chris Packham wrote:
> > Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
> > an integrated CPU (referred to as the CnM block in Marvell's
> > documentation). These have
On Thu, Sep 22, 2022 at 9:40 AM Pali Rohár wrote:
>
> On Thursday 22 September 2022 09:25:37 Chris Packham wrote:
> > On Wed, Sep 21, 2022 at 5:58 PM Stefan Roese wrote:
> > >
> > > On 21.09.22 06:59, Chris Packham wrote:
> > > > Add support for the Alle
On Thu, Sep 22, 2022 at 9:55 AM Pali Rohár wrote:
>
> On Wednesday 21 September 2022 16:59:41 Chris Packham wrote:
> > diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts
> > b/arch/arm/dts/ac5-98dx35xx-rd.dts
> ...
> > +/ {
> > + model = "Marvell RD-AC5X Boar
by default
- remove unnecessary SPI-NOR partitions
Chris Packham (5):
net: mvneta: Add support for AlleyCat5
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
pinctrl: mvebu: Add AlleyCat5 support
arm: mvebu: Support for 98DX25xx/98DX35xx SoC
arm: mvebu: Add RD-AC5X board
a
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
(no changes since v3)
Changes in v3:
- Remove
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
Changes in v4:
- Collect r-by from Stefan
drivers/pinctrl/mvebu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers
t.
Signed-off-by: Chris Packham
---
Changes in v4:
- Remove unused mvebu_get_nand_clock() (will return in a later series)
- Remove unnecessary #ifdefs
- Misc style cleanups
- Replace CONFIG_MVEBU_SAR with simpler code implemented directly in
soc.c based around get_sar_freq which the 32-bit
780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham
---
Changes in v4:
- Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
the defconfig
On Thu, Sep 22, 2022 at 5:18 PM Stefan Roese wrote:
>
> On 22.09.22 05:31, Chris Packham wrote:
> > Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
> > block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
> > the fact that the ac
On Thu, Sep 22, 2022 at 5:10 PM Stefan Roese wrote:
>
> On 22.09.22 05:31, Chris Packham wrote:
> > The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> > features include:
> > * Main 12V/54V power supply
> > * 270 Gbps throughput packet processo
used
Changes in v2:
- Use distro boot by default
- remove unnecessary SPI-NOR partitions
Chris Packham (5):
net: mvneta: Add support for AlleyCat5
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
pinctrl: mvebu: Add AlleyCat5 support
arm: mvebu: Support for 98DX25xx/98DX35xx SoC
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
(no changes since v3)
Changes in v3:
- Remove
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- Collect r-by from Stefan
drivers/pinctrl/mvebu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl
t.
Signed-off-by: Chris Packham
---
Changes in v5:
- Minor fixup for checkpatch.pl complaint
Changes in v4:
- Remove unused mvebu_get_nand_clock() (will return in a later series)
- Remove unnecessary #ifdefs
- Misc style cleanups
- Replace CONFIG_MVEBU_SAR with simpler code implemented directly
780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham
---
Changes in v5:
- Remove unused bpard_{early,late}_init{,_r,_f} functions
- Remove CONFIG_PCI and
pointers). With this change
> fuse command finally works.
>
> Signed-off-by: Pali Rohár
Reviewed-by: Chris Packham
> ---
> arch/arm/mach-kirkwood/include/mach/cpu.h | 3 -
> arch/arm/mach-mvebu/include/mach/cpu.h| 3 -
> arch/arm/mach-mvebu/mbus.c
Hi Pali,
On 23/08/22 11:00, Pali Rohár wrote:
> On Wednesday 17 August 2022 08:17:36 Stefan Roese wrote:
>> On 10.08.22 14:46, Pali Rohár wrote:
>>> mbus driver is initialized from arch_cpu_init() callback which is called
>>> before relocation. This driver stores lot of functions and structure
>>>
).
Tested on an Allied Telesis x530 switch with Micron MT29F2G08ABAEAWP
NAND Flash.
Signed-off-by: Chris Packham
---
This code was taken from the Marvell SDK for the AC5/AC5X integrated
switch/CPU. There are other changes to support the SoC which I will
likely attempt to upstream soon but I think this
cause the physical address of the RAM on the AC5X SoC is
above the 32GiB boundary. As we don't need SMBIOS or EFI this can be
safely disabled.
Signed-off-by: Chris Packham
---
configs/x240_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/x240_defconfig b/configs/x240
se the I2C
offload feature so is not susceptible to the lockup.
We can therefore safely return to using the built-in I2C controller.
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx35xx-atl-x240.dts | 30 ++
configs/x240_defconfig | 1 -
2 files
gpio_request_list_by_name() returns the number of gpios requested.
Notably it swallows the underlying -ENOENT when the "gpios" property
does not exist.
Update the i2c-gpio driver to check for ret == 0 before trying the new
sda-gpios/scl-gpios properties.
Signed-off-by: Chris Packham
controller and avoids
triggering the Errata.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
Changes in v2:
- Update i2c0 alias
- Move i2c-gpio definition to root of device tree
- Remove &i2c0 instead of just disabling it
- Add r-by from Stefan
arch/arm/dts/ac5-98dx35xx-atl-x240.dts
Hi Pierre,
On Sun, Jul 30, 2023 at 6:08 AM Pierre Bourdon wrote:
>
> Chunked raw reads get accumulated to the data buffer, but in some
> ECC configurations they can end up being larger than the originally
> computed size (write page size + OOB size). For example:
>
> 4K page size, ECC strength 8:
On Mon, 31 Jul 2023, 9:29 am Pierre Bourdon, wrote:
> On Sun, Jul 30, 2023 at 11:21 PM Chris Packham
> wrote:
> > On Sun, Jul 30, 2023 at 6:08 AM Pierre Bourdon
> wrote:
> > >
> > > Chunked raw reads get accumulated to the data buffer, but in some
> > >
On Mon, Jul 31, 2023 at 9:29 AM Pierre Bourdon wrote:
>
> On Sun, Jul 30, 2023 at 11:21 PM Chris Packham
> wrote:
> > On Sun, Jul 30, 2023 at 6:08 AM Pierre Bourdon wrote:
> > >
> > > Chunked raw reads get accumulated to the data buffer, but in some
> &g
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