tached hacked together patches to get the system running
and fix up the stack pointer in
normal mode as it pointed to 0.
Best regards
Tim>From ada1a10d612d8f123ff63b17a7b4e5d586a9a43a Mon Sep 17 00:00:00 2001
From: Tim Sander
Date: Mon, 24 Mar 2014 15:12:47 +0100
Subject: [PATCH 1/3] CON
Hi
As i have seen that the Xilinx support has entered master i just tried to boot
it on a Xilinx Zynx Zedboard Rev. D. The build works with the xilinx git tree
so i am pretty confident that its not some issues with bootgen or the embedded
fpga image.
The board loads the fpga which can be seen
Hi Michael, Jagan
Thanks for your replies.
> On Thu, Mar 27, 2014 at 1:51 PM, Michal Simek wrote:
> > Hi,
> >
> > On 03/27/2014 09:08 AM, Tim Sander wrote:
> >> Hi
> >>
> >> As i have seen that the Xilinx support has entered master i just tried
Hi Michal
Am Donnerstag, 27. März 2014, 14:17:41 schrieb Michal Simek:
> Please check and may be you can try u-boot-dtb.elf.
> >>>
> >>> Mh, don't know how to create this kind of file?
> >>
> >> Jagan maybe knows more but I don't think u-boot-dtb.elf is generated.
> >> Just u-boot-dtb.bin i
Hi Michal
> On 03/27/2014 05:32 PM, Tim Sander wrote:
> > Hi Michal
> >
> > Am Donnerstag, 27. März 2014, 14:17:41 schrieb Michal Simek:
> >>>>>> Please check and may be you can try u-boot-dtb.elf.
> >>>>>
> >>>>> Mh,
Hi
> > On 03/27/2014 05:32 PM, Tim Sander wrote:
> > > Hi Michal
> > >
> > > Am Donnerstag, 27. März 2014, 14:17:41 schrieb Michal Simek:
> > >>>>>> Please check and may be you can try u-boot-dtb.elf.
> > >>>>>
>
Hi Albert
> > I am currently trying to configure either Altera Soc and Xilinx Zynq to
> > boot Linux in nonsecure-mode. This mail focusses on the Altera SOC.
> >
> > As soon as the u-boot switched to normal mode it seems there is a problem
> > with code alignment handling? At least it seems the co
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