Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am trying to
make use of the existing spi_flash.c framework available at u-boot for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while using
S25FL256s flash device
wit
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am
trying to
make use of the existing spi_flash.c framework available at u-boot for
erasing/reading/writing
into the flash device.
There are several issues
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am
trying to
make use of the existing spi_flash.c framework
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav Poddar wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav Poddar wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav Poddar
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki
On Monday 17 June 2013 12:44 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:41 PM, Sourav Poddar wrote:
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav Poddar
wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On
Hi Jagan,
On Monday 17 June 2013 01:04 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:49 PM, Sourav Poddar wrote:
On Monday 17 June 2013 12:44 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:41 PM, Sourav Poddar
wrote:
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17
On Monday 17 June 2013 02:09 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 1:11 PM, Sourav Poddar wrote:
Hi Jagan,
On Monday 17 June 2013 01:04 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:49 PM, Sourav Poddar
wrote:
On Monday 17 June 2013 12:44 PM, Jagan Teki wrote:
On Mon, Jun 17
On Monday 17 June 2013 03:28 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 2:15 PM, Sourav Poddar wrote:
On Monday 17 June 2013 02:09 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 1:11 PM, Sourav Poddar
wrote:
Hi Jagan,
On Monday 17 June 2013 01:04 PM, Jagan Teki wrote:
On Mon, Jun 17
, QSPI, and serial flash support
Ravikumar Kattekola (1):
drivers: mtd: qspi: Add quad read support
Sourav Poddar (3):
drivers: mtd: spi: Modify read/write command for sfl256s flash.
driver: spi: Add memory mapped read support
README: qspi usecase and testing documentation.
arch/arm/cpu
From: Matt Porter
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
arch/arm/cpu/armv7/omap5/hw_data.c |7 ++-
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/omap.h |3 +++
arch
, QSPI, and serial flash support
Ravikumar Kattekola (1):
drivers: mtd: qspi: Add quad read support
Sourav Poddar (3):
drivers: mtd: spi: Modify read/write command for sfl256s flash.
driver: spi: Add memory mapped read support
README: qspi usecase and testing documentation.
arch/arm/cpu
Qspi controller has a memory mapped port which can be used for
data transfers. First controller need to be configured through
configuration port, then for data read switch the controller
to memory mapped and read from the predefined location.
Signed-off-by: Sourav Poddar
---
drivers/mtd/spi
From: Matt Porter
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
board/ti/dra7xx/mux_data.h | 10 ++
include/configs/dra7xx_evm.h | 22
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 262 +
2 files changed, 263 insertions(+), 0 deletions
page, if I dont
provide a write disable at the end of the write function.
Signed-off-by: Sourav Poddar
---
drivers/mtd/spi/spi_flash.c | 41 -
1 files changed, 40 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi
Signed-off-by: Sourav Poddar
---
drivers/mtd/spi/spi_flash.c | 110 +-
drivers/mtd/spi/spi_flash_internal.h |2 +
drivers/spi/ti_qspi.c| 18 --
include/configs/dra7xx_evm.h |1 +
include/spi.h
Contains documentation and testing details for qspi flash
interface.
Signed-off-by: Sourav Poddar
---
doc/README.ti_qspi_dra_test | 38 ++
doc/README.ti_qspi_flash| 47 +++
2 files changed, 85 insertions(+), 0
On Wednesday 10 July 2013 06:53 PM, Nishanth Menon wrote:
On Wed, Jul 10, 2013 at 6:25 AM, Sourav Poddar wrote:
From: Matt Porter
Add QSPI definitions and clock configuration support.
OMAP54xx does not have QSPI. DRA7 has QSPI?
Yes.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
On Wednesday 10 July 2013 07:10 PM, Lokesh Vutla wrote:
On Wednesday 10 July 2013 04:55 PM, Sourav Poddar wrote:
From: Matt Porter
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
arch/arm/cpu/armv7/omap5/hw_data.c |7
On Wednesday 10 July 2013 07:13 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 07/10/2013 09:23 AM, Nishanth Menon wrote:
On Wed, Jul 10, 2013 at 6:25 AM, Sourav Poddar
wrote:
From: Matt Porter
I think it's good form to update folks addresses, Matt is now
mat
On Thursday 11 July 2013 05:28 AM, Nishanth Menon wrote:
[...]
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 338a241..2441c55 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -53,5 +53,15 @@ const struct pad_conf_entry
core_padconf_array_e
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Sourav Poddar
---
board/ti/am43xx/mux.c| 11 +++
include/configs/am43xx_evm.h | 20
2 files changed, 31 insertions(+), 0
ils.
This patches are developed and tested on top of the following tree:
git://git.denx.de/u-boot-ti.git
branch: master
Sourav Poddar (5):
am43xx: add qspi support
am437x_epos_evm: add SPL API, QSPI, and serial flash support
qspi/spi: Add AM43xx specifics changes
am43xx: add delay before x
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar
---
arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 +
arch/arm/include/asm/arch-am33xx/cpu.h |4 +++-
arch/arm/include/asm/arch-am33xx/omap.h |1 +
3 files changed, 5 insertions(+), 1 deletions
8100 0xdededede 0x4
U-Boot# sf write 8100 0 0x4
SF: 262144 bytes @ 0x0 Written: OK
U-Boot# sf read 8200 0 0x4
SF: 262144 bytes @ 0x0 Read: OK
U-Boot# md 0x8200
Signed-off-by: Sourav Poddar
---
v1->v2:
- updated commit log with error message.
- Add a FIXME comment in c
This shows the log obtained while testing qspi on AM437x board.
Signed-off-by: Sourav Poddar
---
doc/SPI/README.ti_qspi_am43x_test | 76 +
1 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 doc/SPI/README.ti_qspi_am43x_test
diff --git a
Add AM43xx specific changes.
Signed-off-by: Sourav Poddar
---
drivers/spi/ti_qspi.c | 26 +++---
1 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5a5b482..5666250 100644
--- a/drivers/spi/ti_qspi.c
+++ b
On Friday 20 December 2013 11:56 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/20/2013 01:18 PM, Jagan Teki wrote:
Hi Sourav,
On Fri, Dec 20, 2013 at 11:27 AM, Sourav Poddar wrote:
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done
Hi Jagan,
On Saturday 21 December 2013 12:50 PM, Jagannadha Sutradharudu Teki wrote:
From: Jagannadha Sutradharudu Teki
From: "Poddar, Sourav"
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki
---
V3: Added
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
Discovered the read dummy_cycles based on the configured
read command.
Signed-off-by: Jagannadha Sutradharudu Teki
---
drivers/mtd/spi/sf_internal.h | 2 ++
drivers/mtd/spi/sf_ops.c | 10 ++
drivers/mtd/s
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_op
Signed-off-by: Jagannadha Sutradharudu Teki
---
drivers/mtd/spi/sf_internal.h | 11 ---
dr
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
This a suffix series for
http://u-boot.10912.n7.nabble.com/PATCH-v4-00-36-sf-Add-common-probe-and-extended-quad-read-write-cmds-support-td163949.html
for adding extended read and quad read/write commands support.
Concept:
On Monday 06 January 2014 01:06 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jan 6, 2014 at 12:10 PM, Sourav Poddar wrote:
Hi Jagan,
On Saturday 21 December 2013 12:50 PM, Jagannadha Sutradharudu Teki wrote:
From: Jagannadha Sutradharudu
Teki
From: "Poddar, Sourav"
Add QSPI defin
On Monday 06 January 2014 01:10 PM, Jagan Teki wrote:
On Mon, Jan 6, 2014 at 12:39 PM, Sourav Poddar wrote:
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
QEB code comprises of couple of flash register read/write operations,
this patch moved flash register
On Monday 06 January 2014 03:48 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddar wrote:
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu Teki wrote:
Discovered the read dummy_cycles based on the configured
read command.
Signed-off-by: Jagannadha
On Monday 06 January 2014 04:00 PM, Jagan Teki wrote:
On Mon, Jan 6, 2014 at 3:51 PM, Sourav Poddar wrote:
On Monday 06 January 2014 03:48 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jan 6, 2014 at 12:34 PM, Sourav Poddar
wrote:
On Saturday 04 January 2014 08:34 PM, Jagannadha Sutradharudu
From: Matt Porter
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/omap.h |3 +++
arch
mar Kattekola (1):
drivers: mtd: :spi: Add quad read support
Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
driver: mtd: spi: Add memory mapped read support
README: qspi usecase and testing documentation.
arch/arm/cpu/armv7/omap5/hw_data.c | 10 +-
arch/arm/cpu/armv7/om
support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar
-
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar
---
arch/arm/cpu
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support).
---
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 324
_QUAD" flag. This need to be done because quad read should
only happen when quad command is sent. For reading status register
and other configuration register normal transfers should happen.
Signed-off-by: Ravikumar Kattekola
Signed-off-by: Sourav Poddar
---
drivers/mtd/spi/spi_flash.c
Contains documentation and testing details for qspi flash
interface.
Signed-off-by: Sourav Poddar
---
doc/README.ti_qspi_dra_test | 38 ++
doc/README.ti_qspi_flash| 47 +++
2 files changed, 85 insertions(+), 0
From: Matt Porter
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
board/ti/dra7xx/mux_data.h | 10 ++
include/configs/dra7xx_evm.h | 20
On Thursday 03 October 2013 11:19 PM, Jagan Teki wrote:
Hi Sourav,
Please try to code the driver as specified in below thread!
http://lists.denx.de/pipermail/u-boot/2013-August/160472.html
Ok.
On Fri, Sep 20, 2013 at 8:21 AM, Nobuhiro Iwamatsu
wrote:
Hi,
2013/9/18 Sourav Poddar:
From
prepare a thread for this quad after this release as we did lot
of work last few months back.
Thanks for your help.!!!
Ok.
On Wed, Sep 18, 2013 at 5:51 PM, Sourav Poddar wrote:
This patch series add support for TI qspi controller and in the process also
add support for quad read and memory mapped
Hi Jagan,
If you see the mcspi defconfig(CONFIG_OMAP3_SPI), it is moved to
common file "include/configs/ti_armv7_common.h" . But with this, now after
adding qspi the build breaks like this..
ti_qspi.o: In function `spi_cs_is_valid':
/home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:108: multiple
From: Matt Porter
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/omap.h |3 +++
arch
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar
---
arch/arm/cpu
git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v4
Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support
Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
driver: mtd: spi: Add memory mapped read support
REA
Contains documentation and testing details for qspi flash
interface.
Signed-off-by: Sourav Poddar
---
doc/README.ti_qspi_dra_test | 38 ++
doc/README.ti_qspi_flash| 47 +++
2 files changed, 85 insertions(+), 0
support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support).
---
drivers/spi/Makefile |1 +
drivers/spi/ti_qspi.c | 328
From: Matt Porter
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
board/ti/dra7xx/mux_data.h | 10 ++
include/configs/dra7xx_evm.h | 19
On Saturday 05 October 2013 12:08 AM, Jagan Teki wrote:
Hi Sourav,
Please place these these readme files in doc/SPI/*
All these patches tested on top of u-boot-spi.git master-probe?
Yes, this are tested on the above branch.
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar wrote:
Contains
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar wrote:
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar
wrote:
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral
Poddar wrote:
On Saturday 05 October 2013 12:08 AM, Jagan Teki wrote:
Hi Sourav,
Please place these these readme files in doc/SPI/*
All these patches tested on top of u-boot-spi.git master-probe?
Yes, this are tested on the above branch.
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar
wrote
On Saturday 05 October 2013 01:36 AM, Jagan Teki wrote:
Please use the commit msg head as "sf: .."
Ok.
On Fri, Oct 4, 2013 at 8:21 PM, Sourav Poddar wrote:
Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port r
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddar wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 1:32 AM, Sourav Poddar
wrote:
On Saturday 05 October 2013 12:27 AM, Jagan Teki wrote:
On Fri, Oct 4
On Saturday 05 October 2013 05:10 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 3:25 PM, Sourav Poddar wrote:
On Saturday 05 October 2013 03:11 PM, Jagan Teki wrote:
On Sat, Oct 5, 2013 at 11:38 AM, Sourav Poddar
wrote:
On Saturday 05 October 2013 01:43 AM, Jagan Teki wrote:
On Sat, Oct 5
On Sunday 06 October 2013 03:03 PM, Gerhard Sittig wrote:
On Fri, Oct 04, 2013 at 20:21 +0530, Sourav Poddar wrote:
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index c009af5..bee4128 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -269,7 +269,9
ual
cmd register write happens inside while loop and only when
that write happens, then the cs gets activated.
So, above code does not activate the cs, it just prepare the mask
that will enable cs later.
On Sat, Oct 5, 2013 at 7:53 PM, Sourav Poddar wrote:
On Saturday 05 October 2013 05:10 PM, Jagan Te
On Sunday 06 October 2013 09:00 PM, Jagan Teki wrote:
On Sun, Oct 6, 2013 at 3:44 PM, Sourav Poddar wrote:
On Sunday 06 October 2013 02:14 PM, Jagan Teki wrote:
What if this code is placed in cs_active() with BEGIN flag.?
+ /* setup command reg */
+ qslave->cmd
From: Matt Porter
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/omap.h |3 +++
arch
supports only 16MB access.
Access for higher MB area will be added later.
Patches are available at:
git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v5
Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support
Sourav Poddar (3
support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar
---
arch/arm/cpu
From: Matt Porter
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
board/ti/dra7xx/mux_data.h | 10 ++
include/configs/dra7xx_evm.h | 19
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
[Added quad read support and memory mapped support).
---
v4->v5:
- use tabs wherever required.
- remove stray character in license line
- remove "get_spi_
Contains documentation and testing details for qspi flash
interface.
Signed-off-by: Sourav Poddar
---
v4->v5:
- Move the doc to doc/SPI
- testing details formatted to actual testing logs done on the
board.
doc/SPI/README.ti_qspi_dra_test | 48 +++
doc/
On Monday 07 October 2013 12:33 PM, Jagannadha Sutradharudu Teki wrote:
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
Signed-off-by: Jagannadha
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar
---
arch/arm/cpu
supports only 16MB access.
Access for higher MB area will be added later.
Patches are available at:
git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v7
Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support
Sourav Poddar (3
From: Matt Porter
Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
Signed-off-by: Jagannadha Sutradharudu Teki
---
v5->v6:
- Added ti related comme
From: Matt Porter
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
arch/arm/cpu/armv7/omap5/hw_data.c |8
arch/arm/cpu/armv7/omap5/prcm-regs.c |1 +
arch/arm/include/asm/arch-omap5/omap.h |3 +++
arch
support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar
--
Contains documentation and testing details for qspi flash
interface.
Signed-off-by: Sourav Poddar
---
doc/SPI/README.ti_qspi_dra_test | 48 +++
doc/SPI/README.ti_qspi_flash| 47 ++
2 files changed, 95 insertions
From: Matt Porter
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
---
v5->v6:
change MMAP name to amore readable name.
board/ti/dra7xx/mux_data.h |
On Monday 07 October 2013 05:51 PM, Jagan Teki wrote:
On Wed, Aug 7, 2013 at 8:46 PM, Sourav Poddar wrote:
On Wednesday 07 August 2013 08:35 PM, Jagan Teki wrote:
On Wed, Aug 7, 2013 at 5:34 PM, Sourav Poddar
wrote:
Hi Jagan,
On Wednesday 07 August 2013 05:21 PM, Jagan Teki wrote:
Hi,
On
On Monday 07 October 2013 05:59 PM, Jagan Teki wrote:
On Mon, Oct 7, 2013 at 5:58 PM, Sourav Poddar wrote:
On Monday 07 October 2013 05:51 PM, Jagan Teki wrote:
On Wed, Aug 7, 2013 at 8:46 PM, Sourav Poddar
wrote:
On Wednesday 07 August 2013 08:35 PM, Jagan Teki wrote:
On Wed, Aug 7, 2013
On Monday 07 October 2013 08:01 PM, Jagan Teki wrote:
On Mon, Oct 7, 2013 at 3:52 PM, Sourav Poddar wrote:
This patch series add support for TI qspi controller and in the process also
add support for quad read and memory mapped read
in mtd spi framework.
Testing details:
Did a boot from qspi
asap and let you know. This particular flash
is on another SOC so I will send that SOC specific qspi data after
testing it
with the subject patch.
On Tue, Aug 27, 2013 at 2:48 PM, Jagan Teki wrote:
Hi
On Tue, Aug 27, 2013 at 11:15 AM, Sourav Poddar wrote:
Add support for macronix
debug_dra_qspi
Tested on dra7 evm with qspi boot.
Sourav Poddar (2):
config: dra7_evm: Add Bank Address Register(BAR) config
driver: mtd: sf_ops: claim bus while doing memcpy
drivers/mtd/spi/sf_ops.c |6 ++
include/configs/dra7xx_evm.h |1 +
2 files changed, 7 insertions(+), 0
claim spi bus while doing memory copy, this will set up
the spi controller device control register before doing
a memory read.
Signed-off-by: Sourav Poddar
Tested-by: Yebio Mesfin
---
drivers/mtd/spi/sf_ops.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers
Add config to support bank address register.
Signed-off-by: Sourav Poddar
Tested-by: Yebio Mesfin
---
include/configs/dra7xx_evm.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 1600131..46cc6db 100644
From: Jagannadha Sutradharudu Teki
Signed-off-by: Jagannadha Sutradharudu Teki
Signed-off-by: Sourav Poddar
---
drivers/mtd/spi/sf_probe.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 5eb8ffe..874ef8c
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar
---
arch/arm/cpu/armv7/am33xx/clock_am43xx.c |1 +
arch/arm/include/asm/arch-am33xx/cpu.h |4 +++-
arch/arm/include/asm/arch-am33xx/omap.h |1 +
3 files changed, 5 insertions(+), 1 deletions
Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.
Signed-off-by: Sourav Poddar
---
Hi Jagan,
This patch seems to be necessary for read/write.
I tested by changing few timing variables, but it did not help.
The same
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done:
-
Wrote a uImage to the flash, read it back and boot the
kernel.
Jagannadha Sutradharudu Teki (1):
sf: macronix: Add support for MX25L51235F
Sourav Poddar (4):
am43xx: add qspi support
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Sourav Poddar
---
board/ti/am43xx/mux.c| 11 +++
include/configs/am43xx_evm.h | 20
2 files changed, 31 insertions(+), 0
Add AM43xx specific changes.
Signed-off-by: Sourav Poddar
---
drivers/spi/ti_qspi.c | 26 +++---
1 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5a5b482..5666250 100644
--- a/drivers/spi/ti_qspi.c
+++ b
On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote:
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done:
-
Wrote a uImage to the flash, read it back and boot the
kernel.
Jagannadha Sutradharudu Teki (1):
sf: macronix: Add support for
Hi Jagan,
On Thursday 14 November 2013 09:01 PM, Sourav Poddar wrote:
Hi Jagan,
Here are the miscellaneous fix and config update for dra7 qspi flash.
Patch series adds:
Add BAR config in dra7 config file.
Set spi controller device control registers before
doing a memory mapped read.
Patches
Hi Jagan,
On Thursday 14 November 2013 09:09 PM, Sourav Poddar wrote:
The patch series add support for enabling qspi
on AM43xx at uboot.
Testing done:
-
Wrote a uImage to the flash, read it back and boot the
kernel.
Jagannadha Sutradharudu Teki (1):
sf: macronix: Add support for
On Thursday 19 December 2013 12:21 AM, Jagan Teki wrote:
On Thu, Nov 14, 2013 at 9:09 PM, Sourav Poddar wrote:
From: Jagannadha Sutradharudu Teki
Signed-off-by: Jagannadha Sutradharudu Teki
Signed-off-by: Sourav Poddar
---
drivers/mtd/spi/sf_probe.c |2 ++
1 files changed, 2 insertions
On Thursday 19 December 2013 12:17 AM, Jagan Teki wrote:
On Thu, Nov 14, 2013 at 9:09 PM, Sourav Poddar wrote:
Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.
Signed-off-by: Sourav Poddar
---
Hi Jagan,
This
Jagan,
On Thursday 14 November 2013 09:01 PM, Sourav Poddar wrote:
Hi Jagan,
Here are the miscellaneous fix and config update for dra7 qspi flash.
Patch series adds:
Add BAR config in dra7 config file.
Set spi controller device control registers before
doing a memory mapped read.
Patches
1 - 100 of 142 matches
Mail list logo
