Re: [PATCH v5 5/5] riscv: lib: modify the indent

; Subject: [PATCH v5 5/5] riscv: lib: modify the indent > > We usually use a space in function declaration, rather than a tab. > > Signed-off-by: Zong Li > Reviewed-by: Sean Anderson > --- > arch/riscv/include/asm/cache.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Rick Chen

Re: [PATCH v5 2/5] common: board_r: support enable_caches for RISC-V

n/board_r.c | 4 ++-- > 2 files changed, 6 insertions(+), 2 deletions(-) Reviewed-by: Rick Chen

Re: [PATCH 08/14] lmb: nds32: Add arch_lmb_reserve()

reserve() implemented using arch_lmb_reserve_generic(). > It is rather likely this architecture also needs to cover U-Boot with LMB > before booting Linux. > > Signed-off-by: Marek Vasut > Cc: Rick Chen > Cc: Simon Goldschmidt > Cc: Tom Rini > --- > arch/nds32/lib/bootm.c | 13

Re: [PATCH 09/14] lmb: riscv: Add arch_lmb_reserve()

> > Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic(). > It is rather likely this architecture also needs to cover U-Boot with LMB > before booting Linux. > > Signed-off-by: Marek Vasut > Cc: Atish Patra > Cc: Leo > Cc: Rick Chen > Cc: Simon Goldsc

Re: [PATCH] riscv: Fix setting no-map in reserved memory nodes

9a ("riscv: Provide a mechanism to fix DT for reserved > memory") > Signed-off-by: Samuel Holland > --- > > arch/riscv/lib/fdt_fixup.c | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) Reviewed-by: Rick Chen

Re: [PATCH v2] board: sifive: Fix a potential build warning in board_fdt_blob_setup()

unleashed.c | 4 ++-- > board/sifive/unmatched/unmatched.c | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Rick Chen

Re: [PATCH 1/1] riscv: ae350: enable Coherence Manager for ae350

in the beginning, u-boot-spl would > sometimes fail to boot to u-boot proper. > > Enable CM and I/D cache at the same time in harts_early_init > > Signed-off-by: Leo Yu-Chi Liang > --- > arch/riscv/cpu/ax25/cpu.c | 42 +++ > 1 file changed, 42 insertions(+) Reviewed-by: Rick Chen

Re: [PATCH v6 0/3] Add StarFive JH7110 PCIe drvier support

Hi Minda > From: Minda Chen > Sent: Thursday, June 01, 2023 9:07 AM > To: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志) > ; Simon Glass ; Stefan Roese > ; Andrew Scull ; Pali Rohár > ; Mark Kettenis > Cc: u-boot@lists.denx.de; Mason Huo ; Leyfoon Tan > ; Kevin Xie > Subject: Re: [PATCH v6

Re: [RESEND PATCH v2] riscv: setup per-hart stack earlier

-+ > ++ ==> | hart N-1 stack| > | hart 1 stack |++ > ++| ..| > | ..|| malloc_base | > ++++ > | hart N-1 stack|| GD| > +++----+ &

Re: [RESEND PATCH v1] arch: riscv: jh7110: Correctly zero L2 LIM

-+ > | BSS | <--- cleared by lottery winner hart > ++ 0x804spl_clear_bss (start.S) > | hole | > ++ > | Image+DTB | <--- Assuming cleared/loaded by ROM > ++

Re: [PATCH v1 1/3] riscv: dts: drop microchip from dts filenames

_defconfig | 2 +- > doc/board/microchip/mpfs_icicle.rst | 6 +++--- Reviewed-by: Rick Chen

Re: [PATCH 1/3] riscv: timer: Update the sifive clint timer driver to support aclint

Hi Bin, > From: Bin Meng > Sent: Monday, June 12, 2023 3:36 PM > To: u-boot@lists.denx.de > Cc: Anup Patel ; Atish Patra ; > Bin Meng ; Palmer Dabbelt ; Paul > Walmsley ; Rick Jian-Zhi Chen(陳建志) > > Subject: [PATCH 1/3] riscv: timer: Update the sifive clint timer driver to > support aclint >

Re: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint

> From: Bin Meng > Sent: Monday, June 12, 2023 3:36 PM > To: u-boot@lists.denx.de > Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志) > > Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to > support aclint > > This RISC-V ACLINT specification [1] defines a set of memory

Re: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint

mine whether a syscon based approach needs to be taken to get the > > base address of the ACLINT mswi device. > > > > [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc > > > > Signed-off-by: Bin Meng > > LGTM. Sorry, forgot the signed up. Reviewed-by: Rick Chen > > Thanks, > Rick

Re: [PATCH 3/3] riscv: Rename SiFive CLINT to RISC-V ALINT

fig | 2 +- > board/sipeed/maix/Kconfig | 2 +- > drivers/timer/Makefile| 2 +- > ...ive_clint_timer.c => riscv_aclint_timer.c} | 20 +-- > 14 files changed, 35 insertions(+), 35 deletions(-) rename > arch/riscv/lib/{sifive_c

Re: [PATCH v2 2/3] riscv: dts: sync mpfs-icicle devicetree with linux

| 71 +++ > arch/riscv/dts/mpfs-icicle-kit.dts| 190 +--- > arch/riscv/dts/mpfs.dtsi | 442 -- > .../dt-bindings/clock/microchip-mpfs-clock.h | 29 +- > .../microchip-mpfs-plic.h | 196 > .../interrupt-controller/riscv-hart.h | 17 - Reviewed-by: Rick Chen

Re: [PATCH v5 11/11] board: starfive: Dynamic configuration of DT for 1.2A and 1.3B

spl.c | 157 +++ > 1 file changed, 157 insertions(+) Reviewed-by: Rick Chen

Re: [PATCH v5 10/11] ram: starfive: Read memory size information from EEPROM

> From: Yanhong Wang > Sent: Thursday, June 15, 2023 5:37 PM > To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志) ; Leo > Yu-Chi Liang(梁育齊) ; Joe Hershberger > ; Ramon Fried > Cc: Yanhong Wang ; Torsten Duwe ; > Leyfoon Tan ; samin . guo > ; Walker Chen ; Hal > Feng > Subject: [PATCH v5 10/1

Re: [PATCH v2 1/3] riscv: timer: Update the sifive clint timer driver to support aclint

iscv.h | 2 +- > include/configs/sifive-unleashed.h | 2 +- > include/configs/starfive-visionfive2.h | 1 + > 4 files changed, 14 insertions(+), 7 deletions(-) Reviewed-by: Rick Chen

Re: [PATCH] riscv: Fix alignment of RELA sections in the linker scripts

9a6569a043d3 ("riscv: Update alignment for some sections in linker > scripts") > Signed-off-by: Bin Meng > > --- > This fix should go into the v2023.07 release. > > arch/riscv/cpu/u-boot.lds | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) Reviewed-by: Rick Chen Hi Leo, Please help to push this patch ASAP. Thanks, Rick

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