Hi Anup
>
> Hi Rick,
>
> On Thu, Jul 18, 2019 at 8:27 AM Rick Chen wrote:
> >
> > Hi Anup
> >
> > >
> > > Hi Tom
> > >
> > > > Sent: Thursday, July 18, 2019 1:00 AM
> > > > To: Simon Glass; Rick Jian-Zhi Chen(
rt big endian RISC-V targets as well, the calls to le*_to_cpu
> need to be replaced with macros target*_to_cpu defined by prelink-riscv.c, and
> prelink-riscv.inc included four times (32le, 64le, 32be, 32be) instead of two.
>
> Signed-off-by: Marcus Comstedt
> Cc: Rick Chen
> ---
Hi Anup
>
> On Thu, Jul 18, 2019 at 11:38 AM Rick Chen wrote:
> >
> > Hi Anup
> >
> > >
> > > Hi Rick,
> > >
> > > On Thu, Jul 18, 2019 at 8:27 AM Rick Chen wrote:
> > > >
> > > > Hi Anup
> >
> > From: Anup Patel [mailto:anup.pa...@wdc.com]
> > Sent: Tuesday, June 25, 2019 2:31 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer; Simon Glass
> > Cc: Ramon Fried; Joe Hershberger; Palmer Dabbelt; Paul Walmsley; Troy
> > Benjegerdes; Atish Patra; Alistair Francis; U-Boot Mailing List;
> > From: Anup Patel [mailto:anup.pa...@wdc.com]
> > Sent: Tuesday, June 25, 2019 2:31 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer; Simon Glass
> > Cc: Ramon Fried; Joe Hershberger; Palmer Dabbelt; Paul Walmsley; Troy
> > Benjegerdes; Atish Patra; Alistair Francis; U-Boot Mailing List;
> > From: Anup Patel [mailto:anup.pa...@wdc.com]
> > Sent: Tuesday, June 25, 2019 2:31 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer; Simon Glass
> > Cc: Ramon Fried; Joe Hershberger; Palmer Dabbelt; Paul Walmsley; Troy
> > Benjegerdes; Atish Patra; Alistair Francis; U-Boot Mailing List;
> > From: Anup Patel [mailto:anup.pa...@wdc.com]
> > Sent: Tuesday, June 25, 2019 2:31 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer; Simon Glass
> > Cc: Ramon Fried; Joe Hershberger; Palmer Dabbelt; Paul Walmsley; Troy
> > Benjegerdes; Atish Patra; Alistair Francis; U-Boot Mailing List;
> > From: Anup Patel [mailto:anup.pa...@wdc.com]
> > Sent: Tuesday, June 25, 2019 2:32 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer; Simon Glass
> > Cc: Ramon Fried; Joe Hershberger; Palmer Dabbelt; Paul Walmsley; Troy
> > Benjegerdes; Atish Patra; Alistair Francis; U-Boot Mailing List;
> > From: Anup Patel [mailto:anup.pa...@wdc.com]
> > Sent: Tuesday, June 25, 2019 2:32 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer; Simon Glass
> > Cc: Ramon Fried; Joe Hershberger; Palmer Dabbelt; Paul Walmsley; Troy
> > Benjegerdes; Atish Patra; Alistair Francis; U-Boot Mailing List;
> > From: Anup Patel [mailto:anup.pa...@wdc.com]
> > Sent: Tuesday, June 25, 2019 2:32 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer; Simon Glass
> > Cc: Ramon Fried; Joe Hershberger; Palmer Dabbelt; Paul Walmsley; Troy
> > Benjegerdes; Atish Patra; Alistair Francis; U-Boot Mailing List;
> > From: Anup Patel [mailto:anup.pa...@wdc.com]
> > Sent: Wednesday, July 17, 2019 12:24 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer; Peng Fan; Jagan Teki;
> > Oleksandr Zhadan and Michael Durrant
> > Cc: Palmer Dabbelt; Paul Walmsley; Atish Patra; Anup Patel; Bhargav Shah;
> > U-Boot
> > From: Anup Patel [mailto:anup.pa...@wdc.com]
> > Sent: Wednesday, July 17, 2019 12:24 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer; Peng Fan; Jagan Teki;
> > Oleksandr Zhadan and Michael Durrant
> > Cc: Palmer Dabbelt; Paul Walmsley; Atish Patra; Anup Patel; Bhargav Shah;
> > U-Boot
Hi Lukas
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Tuesday, February 12, 2019 6:14 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer Dabbelt;
> > Alexander Graf; Lukas Auer; Anup Patel; Rick Jian-Zhi Chen(陳建志); Baruch
>
up Patel wrote:
> > > > -Original Message-
> > > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > > > Sent: Tuesday, February 12, 2019 3:44 AM
> > > > To: u-boot@lists.denx.de
> > > > Cc: Atish Patra ; Anup Patel
Hi Anup
Anup Patel 於 2019年2月21日 週四 下午5:57寫道：
>
> On Thu, Feb 21, 2019 at 11:31 AM Bin Meng wrote:
> >
> > On Thu, Feb 21, 2019 at 12:48 PM Anup Patel wrote:
> > >
> > > Hi Rick,
> > >
> > > On Fri, Feb 15, 2019 at 10:19 AM Rick Chen wro
Hi Anup
Rick Chen 於 2019年2月22日 週五 下午12:05寫道：
>
> Hi Anup
>
> Anup Patel 於 2019年2月21日 週四 下午5:57寫道：
>
> >
> > On Thu, Feb 21, 2019 at 11:31 AM Bin Meng wrote:
> > >
> > > On Thu, Feb 21, 2019 at 12:48 PM Anup Patel wrote:
> > > >
> >
Hi Anup
Anup Patel 於 2019年2月25日 週一 上午11:28寫道：
>
> On Mon, Feb 25, 2019 at 7:50 AM Rick Chen wrote:
> >
> > Hi Anup
> >
> > Rick Chen 於 2019年2月22日 週五 下午12:05寫道：
> > >
> > > Hi Anup
> > >
> > > Anup Patel 於 2019年2月21日 週四 下午5:57寫
Hi Anup
Anup Patel 於 2019年2月26日 週二 下午7:55寫道：
>
> On Mon, Feb 25, 2019 at 12:50 PM Rick Chen wrote:
> >
> > Hi Anup
> >
> > Anup Patel 於 2019年2月25日 週一 上午11:28寫道：
> > >
> > > On Mon, Feb 25, 2019 at 7:50 AM Rick Chen wrote:
> > > >
>
Hi Lukas
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Tuesday, February 12, 2019 6:14 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer Dabbelt;
> > Alexander Graf; Lukas Auer; Anup Patel; Rick Jian-Zhi Chen(陳建志); Baruch
>
Hi Lukas
Auer, Lukas 於 2019年3月11日 週一 上午2:12寫道：
>
> On Sun, 2019-03-10 at 20:24 +0530, Anup Patel wrote:
> > On Sun, Mar 10, 2019 at 7:28 PM Auer, Lukas
> > wrote:
> > > Hi Rick,
> > >
> > > On Thu, 2019-03-07 at 17:30 +0800, Rick Chen wrote:
> >
er a0 with the hart ID from the mhartid CSR to avoid possible
> > problems on
> > RISC-V processors with a boot ROM that does not handle this task.
> >
> > Suggested-by: Rick Chen
> > Signed-off-by: Lukas Auer
> > ---
> >
> > Changes in v2:
> >
Hi Lukas
> Hi Rick,
>
> On Wed, 2019-08-14 at 20:15 +, Auer, Lukas wrote:
> > Hi Rick,
> >
> > On Wed, 2019-08-14 at 10:20 +0800, Rick Chen wrote:
> > > Hi Lukas
> > >
> > > > > From: Tom Rini [mailto:tr...@konsulko.com]
> >
Hi Bin
> Hi Rick,
>
> On Wed, Aug 21, 2019 at 4:15 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > The L2 cache will be enabled in init flow of dm cache
> > driver when it detect L2 node in dtb.
> >
> > When U-Boot jumps to Linux Kernel, the
Hi Bin
> Hi Rick,
>
> On Wed, Aug 21, 2019 at 4:16 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > Add L2 cache enable and disable ops for test coverage.
>
> It's not L2 cache for Sandbox. Please rewrite the commit message.
I will remove L2 and re
Hi Bin
> Hi Rick,
>
> On Wed, Aug 21, 2019 at 4:16 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > Add a v5l2 cache controller driver that is usually found on
> > Andes RISC-V ae350 platform. It will parse the cache settings
> > from the dtb.
>
Hi Hannes
> > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Hannes
> > Schmelzer
> > Sent: Thursday, August 22, 2019 6:21 PM
> > To: U-Boot Mailing List
> > Subject: [U-Boot] toolchain for riscv?
> >
> > hi,
> >
> > just tried to run moveconfig.py, having trouble to find the tool
t; #define CONFIG_SPL_STACK (0x0800 + 0x001D - \
> > > > GENERATED_GBL_DATA_SIZE)
> > >
> > > What caused this?
> > >
> > > Last time this was seen on Ax25-AE350, CONFIG_SPL_SYS_MALLOC_F_LEN
> > >
Hi, Bin
> Hi Rick,
>
> On Mon, Oct 25, 2021 at 9:49 AM Rick Chen wrote:
> >
> > Hi Bin,
> >
> > > From: Bin Meng
> > > Sent: Tuesday, October 19, 2021 4:55 PM
> > > To: Alexandre Ghiti
> > > Cc: Heinrich Schuchardt ; Tom Rini
Hi Jagon
> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> Sent: Monday, November 18, 2019 7:30 PM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: u-boot@lists.denx.de; Jagan Teki
> Subject: [PATCH v4 2/2] sifive: fu540: Enable OF_SEPARATE
>
> Use dts support from U-Boot via OF_SEPARATE instead of depe
Hi Lukas
> From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> Sent: Wednesday, December 04, 2019 5:40 AM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; Lukas Auer; Anup Patel;
> Atish Patra
> Subject: [PATCH 2/4] riscv: add functions for reading the IPI st
r file include/opensbi.h is synchronized with
> include/sbi/fw_dynamic.h from the OpenSBI project to update the info
> structure. The header file is recent as of commit
> 7a13beb21326 ("firmware: Add preferred boot HART field in struct
> fw_dynamic_info").
>
> Reported-by: Rick C
HI Lukas
> From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> Sent: Wednesday, December 04, 2019 5:40 AM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; Lukas Auer; Anup Patel;
> Anup Patel; Atish Patra; Marcus Comstedt
> Subject: [PATCH 0/4] Fixes for RISC
nt to be able to judge when the request has been
> completed. Remove the delay by clearing the IPI after cache invalidation and
> just before calling the function from the request.
>
> Signed-off-by: Lukas Auer
> ---
>
Reviewed-by: Rick Chen
Tested-by: Rick Chen
> arch/riscv/cpu/s
as reported that
> this assumption is not always correct.
>
> To make sure the assumption always holds true, wait for all secondary harts
> to acknowledge the call-function request before entering OpenSBI on the main
> hart.
>
> Reported-by: Rick Chen
> Signed-off-b
> Interruptor (CLINT).
>
> Signed-off-by: Lukas Auer
> ---
>
> Changes in v2:
> - Use the pending register instead of the claim register in the Andes PLIC
> implementation
>
Reviewed-by: Rick Chen
> arch/riscv/lib/andes_plic.c | 11 +++
> arch/riscv/
arch/riscv/lib/interrupts.c index
> 3b25c5b7a7..0f1e5123d2 100644
> --- a/arch/riscv/lib/interrupts.c
> +++ b/arch/riscv/lib/interrupts.c
> @@ -5,6 +5,8 @@
> *
> * Copyright (C) 2017 Andes Technology Corporation
> * Rick Chen, Andes Technology Corporation
> + *
> + *
>
> Provide function sbi_get_impl_version() to retrieve the SBI implementation
> version.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/include/asm/sbi.h | 1 +
> arch/riscv/lib/sbi.c | 19 +++
> 2 files changed, 20 insertions(+)
Reviewed-by: Rick Chen
show the SBI implementation version
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/sbi.c | 26 ++
> 1 file changed, 18 insertions(+), 8 deletions(-)
Reviewed-by: Rick Chen
> include/configs/imx8qxp_mek.h | 2 --
> 8 files changed, 2 insertions(+), 15 deletions(-)
Reviewed-by: Rick Chen
/include/linux/kconfig.h,
> CONFIG_IS_ENABLED(OF_BOARD) expands to 0 when CONFIG_SPL_BUILD is defined
> because there is no CONFIG_SPL_OF_BOARD.
>
> Use #if defined instead.
>
> Signed-off-by: Leo Yu-Chi Liang
> ---
> board/AndesTech/ax25-ae350/ax25-ae350.c | 4 ++--
> 1 file changed,
> Hi Rick,
>
> On Mon, Oct 25, 2021 at 10:24 AM Rick Chen wrote:
> >
> > Hi, Bin
> >
> > > Hi Rick,
> > >
> > > On Mon, Oct 25, 2021 at 9:49 AM Rick Chen wrote:
> > > >
> > > > Hi Bin,
> > > >
> >
"
>
> echo $cmd
> eval $cmd
> }
>
> The address where the kernel is loaded can be altered by changing the value
> of KERNEL_IMAGE_ADDR.
>
> Signed-off-by: Leo Yu-Chi Liang
> ---
> include/configs/ax25-ae350.h | 13 -
> 1 file changed, 12 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
f-by: Anup Patel
> Reviewed-by: Philipp Tomsich
> ---
> drivers/serial/Kconfig | 8 ++
> drivers/serial/Makefile | 1 +
> drivers/serial/serial_htif.c | 178 +++
> 3 files changed, 187 insertions(+)
Reviewed-by: Rick Chen
console support
>
> Enable support for HTIF console so that we can use QEMU RISC-V U-Boot on
> RISC-V emulators and ISS having it.
>
> Signed-off-by: Anup Patel
> Reviewed-by: Philipp Tomsich
> ---
> board/emulation/qemu-riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rick Chen
or qemu-riscv board which will return 1
> only if CFI flash DT node is present.
>
> Fixes: d248627f9d42 ("riscv: qemu: Enable MTD NOR flash support")
> Signed-off-by: Anup Patel
> ---
> board/emulation/qemu-riscv/qemu-riscv.c | 17 +++++
> 1 file changed, 17 insertions(+)
Reviewed-by: Rick Chen
Hi Pragnesh
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Friday, September 11, 2020 2:48 PM
> To: Pragnesh Patel
> Cc: U-Boot Mailing List; Atish Patra; Anup Patel; Sagar Kadam; Rick Jian-Zhi
> Chen(陳建志); Paul Walmsley; Bin Meng; Lukas Auer; Sean Anderson
> Subject: Re: [PATCH 1/3] riscv:
an-Zhi Chen(陳建志);
> Pragnesh Patel; Bin Meng; Jagan Teki; Sean Anderson
> Subject: [PATCH] riscv: fu540: dts: Correct reg size of clint node
>
> Signed-off-by: Pragnesh Patel
> ---
> arch/riscv/dts/fu540-c000-u-boot.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
e Moal
> Signed-off-by: Sean Anderson
> ---
>
> arch/riscv/dts/k210.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Rick Chen
Hi Sean
> On 10/13/20 8:43 PM, Rick Chen wrote:
> >> Half of this driver is a DM-based timer driver, and half is RISC-V-specific
> >> IPI code. Move the timer portions in with the other timer drivers. The
> >> KConfig is not moved, since it also enables IPIs. It cou
rl-kendryte.c
> @@ -55,8 +55,9 @@
>
Reviewed-by: Rick Chen
10 +-
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
Reviewed-by: Rick Chen
k/kendryte/pll.c | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Rick Chen
2:
> - New
>
> drivers/clk/kendryte/pll.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Rick Chen
> These devices are necessary for the clock driver, which is required by the
> sram driver, to run pre-relocation.
>
> Signed-off-by: Sean Anderson
> ---
>
> (no changes since v1)
>
> arch/riscv/dts/k210.dtsi | 4
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Rick Chen
0 +-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
Reviewed-by: Rick Chen
son
> Reviewed-by: Simon Glass
> ---
>
> (no changes since v1)
>
> include/fdtdec.h | 19 ++-
> lib/fdtdec.c | 34 +-
> 2 files changed, 47 insertions(+), 6 deletions(-)
>
Reviewed-by: Rick Chen
changed, 65 insertions(+)
> create mode 100644 drivers/ram/kendryte.c
>
Reviewed-by: Rick Chen
> Other RISC-V targets should not have RAM_SIFIVE enabled by default.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Pragnesh Patel
> ---
>
> (no changes since v1)
>
> drivers/ram/sifive/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Rick Chen
;
> arch/riscv/cpu/generic/dram.c | 26 ++
> 1 file changed, 26 insertions(+)
>
Reviewed-by: Rick Chen
)
>
> board/sipeed/maix/Kconfig | 2 ++
> board/sipeed/maix/maix.c | 26 --
> configs/sipeed_maix_bitm_defconfig | 1 +
> include/configs/sipeed-maix.h | 4
> 4 files changed, 3 insertions(+), 30 deletions(-)
>
Reviewed-by: Rick Chen
tions(+), 2 deletions(-)
>
Reviewed-by: Rick Chen
; 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Rick Chen
; >> ---
> >> arch/riscv/lib/crt0_riscv_efi.S | 7 ++-
> >> 1 file changed, 6 insertions(+), 1 deletion(-)
> >>
Reviewed-by: Rick Chen
> >> diff --git a/arch/riscv/lib/crt0_riscv_efi.S
> >b/arch/riscv/lib/crt0_riscv_efi.S
> >> index 8
rror
> >> riscv: Add watchdog bindings for the k210
> >> riscv: Enable watchdog for the k210
> >>
> >> arch/riscv/dts/k210.dtsi | 1 -
> >> board/sipeed/maix/Kconfig | 2 ++
> >> drivers/watchdog/designware_wdt.c | 39 -------
llow attaching a virtual SATA disk to qemu-riscv64_defconfig.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> configs/qemu-riscv64_defconfig | 6 ++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Rick Chen
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> Sent: Thursday, November 05, 2020 7:31 PM
> To: u-boot@lists.denx.de
> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick
> Jian-Zhi Chen(陳建
Hi Pragnesh
> Hi Rick,
>
> >-Original Message-----
> >From: Rick Chen
> >Sent: 09 November 2020 13:44
> >To: Pragnesh Patel
> >Cc: U-Boot Mailing List ; Atish Patra
> >; Bin Meng ; Paul Walmsley (
> >Sifive) ; Anup Patel ; Sagar
> &
> - Update the Opencores I2C Controller Link
>
> drivers/i2c/Kconfig | 7 +
> drivers/i2c/Makefile | 1 +
> drivers/i2c/ocores_i2c.c | 636 +++
> 3 files changed, 644 insertions(+)
> create mode 100644 drivers/i2c/ocores_i2c.c
>
Reviewed-by: Rick Chen
ller.
>
> Signed-off-by: Pragnesh Patel
> ---
>
> (no changes since v1)
>
> arch/riscv/cpu/fu540/Kconfig | 2 ++
> board/sifive/fu540/Kconfig | 1 +
> 2 files changed, 3 insertions(+)
>
Reviewed-by: Rick Chen
Signed-off-by: Pragnesh Patel
> > ---
> >
> > Changes in v2:
> > - Remove TYPE_SIFIVE_REV0 flag
> > - Update the Opencores I2C Controller Link
> >
> > drivers/i2c/Kconfig | 7 +
> > drivers/i2c/Makefile | 1 +
> > drivers/i2c/ocore
00644
> > --- a/drivers/pinctrl/pinctrl-kendryte.c
> > +++ b/drivers/pinctrl/pinctrl-kendryte.c
> > @@ -55,8 +55,9 @@
> >
>
> Reviewed-by: Rick Chen
Please check about the CI failure items:
https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/742884254
+drivers
Hi Pragnesh
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> Sent: Wednesday, November 11, 2020 6:15 PM
> To: u-boot@lists.denx.de
> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick
> Ji
Hi Pragnesh
> Hi Rick,
>
> >-Original Message-----
> >From: Rick Chen
> >Sent: 13 November 2020 13:37
> >To: Pragnesh Patel
> >Cc: U-Boot Mailing List ; Atish Patra
> >; palmerdabb...@google.com; Bin Meng
> >; Paul Walmsley ( Sifive) ;
>
HI Anup,
> From: Anup Patel
> Sent: Sunday, February 06, 2022 4:41 PM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: Bin Meng ; Atish Patra ;
> Alistair Francis ; Anup Patel
> ; U-Boot Mailing List
> Subject: Re: [PATCH v2 0/4] QEMU spike machine support for U-Boot
>
> Hi Rick,
>
> On Thu, Jan 27, 2022
Hi Bin
> -Original Message-
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, May 19, 2020 4:44 PM
> To: Pragnesh Patel; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
>
> Hi Rick,
>
> On Tue, May 19, 2020 at 3:04 PM Pragnesh Patel
>
t_dm. In SPL, it is
> called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions
> should be called.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Rick Chen
> ---
>
> Changes in v11:
> - Initialize IPI when used by SPL
> Changes in v9:
> - Fix typ
Hi Sean
>
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a
> "KPU" neural network processor, an audio processor supportin
Hi Tom
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Monday, May 25, 2020 11:40 PM
> To: Open Source Project uboot
> Cc: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>
> On Mon, May 25, 2020 at 04:01:08PM +0800, ub...@andestech.com
in Meng
>
> The copy of reserved memory node from source dtb to destination dtb can be
> avoided if they point to the same place. This is useful when OF_PRIOR_STAGE
> is used.
>
> Signed-off-by: Bin Meng
> ---
Reviewed-by: Rick Chen
>
> arch/riscv/lib/fdt_fixup.c | 12
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Wednesday, May 20, 2020 3:40 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Bin Meng
> Subject: [PATCH 2/2] riscv: Enable CONFIG_OF_BOARD_FIXUP by default
>
> From: Bin Meng
>
> Starting from OpenSBI v0.7, the SBI firmware i
Hi Bin
> Hi Rick,
>
> On Thu, May 28, 2020 at 4:17 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > Sent: Wednesday, May 20, 2020 3:40 PM
> > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing Li
Hi Bin
> Hi Rick,
>
> On Thu, May 28, 2020 at 4:24 PM Bin Meng wrote:
> >
> > Hi Rick,
> >
> > On Thu, May 28, 2020 at 4:17 PM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > > From: Bin Meng [mailto:bmeng...@gmail.com]
>
> sbi_probe_extension() is an API defined in SBI v0.2, not v0.1.
>
> Fixes 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to SBI_v01")
> Signed-off-by: Bin Meng
> ---
Reviewed-by: Rick Chen
>
> arch/riscv/lib/sbi.c | 37 +++--
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Wednesday, May 27, 2020 5:05 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Atish Patra; Bin Meng
> Subject: [PATCH 1/2] riscv: sbi: Remove sbi_spec_version
>
> From: Bin Meng
>
> U-Boot defaults to use SBI v0.2. Howerver th
ONFIG_SBI_V01
> >
> > From: Bin Meng
> >
> > sbi_probe_extension() is an API defined in SBI v0.2, not v0.1.
> >
> > Fixes 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to SBI_v01")
> > Signed-off-by: Bin Meng
> > ---
>
Hi Bin
> Hi Rick,
>
> On Mon, Jun 1, 2020 at 3:40 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > Hi Rick,
> > >
> > > On Thu, May 28, 2020 at 4:24 PM Bin Meng wrote:
> > > >
> > > > Hi Rick,
> > >
Hi Bin
> Hi Rick,
>
> On Mon, Jun 1, 2020 at 3:36 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > Hi Rick,
> > >
> > > On Thu, May 28, 2020 at 4:17 PM Rick Chen wrote:
> > > >
> > > > Hi Bin
> > > >
> &g
Hi Bin
Bin Meng 於 2020年6月2日 週二 下午2:13寫道：
>
> Hi Rick,
>
> On Tue, Jun 2, 2020 at 2:04 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > Hi Rick,
> > >
> > > On Mon, Jun 1, 2020 at 3:36 PM Rick Chen wrote:
> > > >
> > > &
Hi Bin
Bin Meng 於 2020年6月2日 週二 下午2:33寫道：
>
> Hi Rick,
>
> On Tue, Jun 2, 2020 at 2:16 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > Bin Meng 於 2020年6月2日 週二 下午2:13寫道：
> > >
> > > Hi Rick,
> > >
> > > On Tue, Jun 2, 2020 at 2:
Hi Bin
Bin Meng 於 2020年6月1日 週一 下午5:06寫道：
>
> Hi Rick,
>
> On Mon, Jun 1, 2020 at 4:14 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > Sent: Wednesday, May 27, 2020 5:05 PM
> > > To: Rick Jian
Hi Atish
Atish Patra 於 2020年6月3日 週三 上午2:22寫道：
>
> On Mon, Jun 1, 2020 at 11:51 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > Bin Meng 於 2020年6月2日 週二 下午2:33寫道：
> > >
> > > Hi Rick,
> > >
> > > On Tue, Jun 2, 2020 at 2:16 PM Rick Che
Hi Atish
Atish Patra 於 2020年6月3日 週三 上午2:32寫道：
>
> On Mon, Jun 1, 2020 at 2:09 AM Bin Meng wrote:
> >
> > Hi Rick,
> >
> > On Mon, Jun 1, 2020 at 5:08 PM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > > > From: Bin Meng
Hi Bin
Bin Meng 於 2020年6月2日 週二 下午5:39寫道：
>
> Hi Rick,
>
> On Tue, Jun 2, 2020 at 5:13 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > Bin Meng 於 2020年6月1日 週一 下午5:06寫道：
> > >
> > > Hi Rick,
> > >
> > > On Mon, Jun 1, 2020 at
Hi Jagan
> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> Sent: Wednesday, June 03, 2020 2:57 AM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: U-Boot-Denx; Atish Patra; Palmer Dabbelt; Bin Meng; Paul Walmsley; Anup
> Patel; Sagar Kadam; Pragnesh Patel
> Subject: Re: [PATCH v13 00/19] RISC-V SiFive
; Cc: Daniel Schwierzeck
> Cc: Leo
> Cc: Palmer Dabbelt
> Cc: Paul Walmsley
> Cc: Rick Chen
> Cc: Sean Anderson
> Cc: Simon Glass
> Signed-off-by: Tom Rini
> ---
> I'm Cc'ing a bunch of RISC-V folks since that's where I'm least confident and
>
; ---
For riscv,
Reviewed-by: Rick Chen
.c | 75 +
> 3 files changed, 83 insertions(+)
> create mode 100644 drivers/cache/cache-sifive-ccache.c
Reviewed-by: Rick Chen
> From: Zong Li
> Sent: Tuesday, August 31, 2021 5:21 PM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; bmeng...@gmail.com; sean...@gmail.com;
> green@sifive.com; paul.walms...@sifive.com; s...@chromium.org;
> u-boot@lists.denx.de
> Cc: Zong Li
> Subject: [PATCH v4 2/4] riscv: l
rface of cache
> uclass to execute the relative implementation in SiFive ccache driver.
>
> Signed-off-by: Zong Li
> ---
> arch/riscv/Kconfig| 5 +
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/sifive_cache.c | 27 +++++++
> 3 files changed, 33 insertions(+)
Reviewed-by: Rick Chen
-
> arch/riscv/include/asm/arch-fu540/cache.h | 14 --
> arch/riscv/include/asm/arch-fu740/cache.h | 14 --
> board/sifive/unleashed/unleashed.c| 10 +----
> board/sifive/unmatched/unmatched.c| 11 ++---
Reviewed-by: Rick Chen
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