ch/riscv/lib/rdtime.c | 38
> drivers/timer/Kconfig | 6 +++---
> drivers/timer/riscv_timer.c | 39 +++--
> 5 files changed, 23 insertions(+), 69 deletions(-)
> delete mode 100644 arch/riscv/lib/rdtime.c
>
Reviewed-by: Rick Chen
struct ipi_data ipi[CONFIG_NR_CPUS];
> #endif
> diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
> index a7e90ca992..b0245d0b52 100644
> --- a/arch/riscv/lib/andes_plmt.c
> +++ b/arch/riscv/lib/andes_plmt.c
> @@ -1,6 +1,7 @@
> // SPDX-License
Hi Sean
> On the K210, the prior stage bootloader does not clear IPIs. This presents
> a problem, because U-Boot up until this point assumes (with one exception)
> that IPIs are cleared when it starts. This series attempts to fix this in a
> robust manner, and fix several concurrency bugs I notice
Hi Sean
> Clearing MIP doesn't do anything. Whoops. The following commits should
> tackle this problem in a more robust manner.
I still not catch your points about that this commit 947263033 really
help to fix pending IPIs not clean problem on k210 platform at that
time, but you just said it do
Hi Sean
> Some IPIs may already be pending when U-Boot is started. This could be a
> problem if a secondary hart tries to handle an IPI before the boot hart has
> initialized the IPI device.
>
> This commit uses NULL as a sentinel for secondary harts so they know when
> the IPI is initialized, and
Hi Sean
> Hi Sean
>
> > Some IPIs may already be pending when U-Boot is started. This could be a
> > problem if a secondary hart tries to handle an IPI before the boot hart has
> > initialized the IPI device.
> >
> > This commit uses NULL as a sentinel for secondary harts so they know when
> > the
Hi Sean
> Without these fences, it is perfectly valid for an out-of-order core to
> re-order memory accesses to outside of the available_harts_lock critical
> section.
>
> Signed-off-by: Sean Anderson
> ---
>
> arch/riscv/cpu/start.S | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Hi Sean
> On 9/9/20 3:50 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> Clearing MIP doesn't do anything. Whoops. The following commits should
> >> tackle this problem in a more robust manner.
> >
> > I still not catch your points about that this com
Hi Sean
> On 9/8/20 10:02 PM, Rick Chen wrote:
> > Hi Sean
> >
> >> On the K210, the prior stage bootloader does not clear IPIs. This presents
> >> a problem, because U-Boot up until this point assumes (with one exception)
> >> that IPIs are cleared w
Hi Sean
> On 9/9/20 5:01 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> Hi Sean
> >>
> >>> Some IPIs may already be pending when U-Boot is started. This could be a
> >>> problem if a secondary hart tries to handle an IPI before
HI Sean
> On 9/11/20 10:45 AM, Bin Meng wrote:
> > On Fri, Sep 11, 2020 at 6:22 PM Sean Anderson wrote:
> >>
> >> On 9/11/20 3:38 AM, Bin Meng wrote:
> >>> Hi Sean,
> >>>
> >>> On Tue, Sep 8, 2020 at 2:17 AM Sean Anderson wrote:
>
> Clearing MIP doesn't do anything. Whoops. The followi
Hi Sean
> On 9/9/20 5:01 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> Hi Sean
> >>
> >>> Some IPIs may already be pending when U-Boot is started. This could be a
> >>> problem if a secondary hart tries to handle an IPI before
for CPUs which previously only enabled them for the
> > boot hart. I think ax25 is the only CPU which currently does this. Bin,
> > would this be an issue?
No, they are functions shall be called in different stage about lottery.
riscv_hart_early_init() is called before lottery for
nds32 still uses its own private bd_info struct. Move it over to
> use the generic one like other archs.
>
> Signed-off-by: Simon Glass
> ---
>
Reviewed-by: Rick Chen
> arch/nds32/include/asm/u-boot.h | 20 ++--
> 1 file changed, 2 insertions(+), 18 deletions
s own private bd_info struct. Move it over to
> use the generic one like other archs.
>
> Signed-off-by: Simon Glass
> ---
>
Reviewed-by: Rick Chen
> arch/riscv/include/asm/u-boot.h | 19 ++-
> 1 file changed, 2 insertions(+), 17 deletions(-)
>
> diff -
t; This arch has none of its own info to show. Move it over to use the generic
> do_bdinfo().
>
> Signed-off-by: Simon Glass
> ---
>
Reviewed-by: Rick Chen
> cmd/bdinfo.c | 14 +-
> 1 file changed, 1 insertion(+), 13 deletions(-)
>
> diff --git a/cmd/bdin
h has none of its own info to show. Move it over to use the generic
> do_bdinfo().
>
> Signed-off-by: Simon Glass
> ---
>
Reviewed-by: Rick Chen
> cmd/bdinfo.c | 15 +--
> 1 file changed, 1 insertion(+), 14 deletions(-)
>
> diff --git a/cmd/bdinfo.c b/
t_dm. Before this
> point, no riscv_*_ipi functions should be called.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Rick Chen
> ---
>
> Changes in v9:
> - Fix type of ret variable in riscv_ipi_init
> Changes in v7:
> - Split IPI clearing off into its own patch
Hi Sean
> This patch adds documentation for the Sipeed Maix bit, and more generally
> for the Kendryte K210 processor.
>
> Signed-off-by: Sean Anderson
> ---
>
> Changes in v9:
> - Mark dts code block as "none" explicitly
> Changes in v7:
> - Split off into its own patch
> - Fix size of clint
>
>
Hi Sean
> On 5/5/20 1:02 PM, Sean Anderson wrote:
> > On 5/5/20 5:01 AM, Rick Chen wrote:
> >> Hi Sean
> >>
> >>> This patch adds documentation for the Sipeed Maix bit, and more generally
> >>> for the Kendryte K210
esh Patel ; U-Boot Mailing List >b...@lists.denx.de>; Atish Patra ; Palmer Dabbelt
> >; Paul Walmsley ;
> >Jagan Teki ; Troy Benjegerdes
> >; Anup Patel ; Sagar
> >Kadam ; Rick Chen ; Palmer
> >Dabbelt
> >Subject: Re: [PATCH v5 12/14] riscv: sifive: fu540: e
Before this
> point, no riscv_*_ipi functions should be called.
>
> Signed-off-by: Sean Anderson
Reviewed-by: Rick Chen
em, ensuring
> that only one hart modifies shared memory at once.
>
> Signed-off-by: Sean Anderson
> ---
Reviewed-by: Rick Chen
some of our cases of
> adding different bit/endian linker flags via ldflags-y
>
> Cc: Rick Chen
> Signed-off-by: Tom Rini
> ---
> arch/riscv/config.mk | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
Reviewed-by: Rick Chen
.
Hi Jagan
> clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean
> predicate instead of the index. Other clk_get_by_* functions got the clock
> correctly, but passed a predicate instead of the index to clk_get_by_tail.
> This could lead to confusing error messages.
>
> Signed-
Hi Peng and Lukasz
> This patch adds alternate versions of the clk_*_register functions for use
> with statically-allocated struct clks. This allows drivers to define clocks
> at compile-time and register them at run-time without malloc-ing. This
> increases the size of the binary, but should not
Hi Sean
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a
> "KPU" neural network processor, an audio processor supporting
during arch_cpu_init_dm. Before this
> > point, no riscv_*_ipi functions should be called.
> >
> > Signed-off-by: Sean Anderson
>
> Reviewed-by: Rick Chen
conflict with u-boot/master, please rebase
Thanks
Rick
Applying: riscv: Clean up IPI initialization code
error: patc
Hi Bin,
> Hi Rick,
>
> On Mon, May 10, 2021 at 3:22 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > Hi Bin,
> > >
> > > > From: Bin Meng
> > > > Sent: Monday, May 10, 2021 2:58 PM
> > > > To: Simon Glass ; Rick Ji
+++
> tools/binman/etype/opensbi.py | 23 +++
> tools/binman/ftest.py | 7 +++
> tools/binman/test/201_opensbi.dts | 14 ++
> 4 files changed, 57 insertions(+)
Reviewed-by: Rick Chen
> Hi Rick,
>
> On Tue, May 11, 2021 at 8:49 AM Rick Chen wrote:
> >
> > Hi Bin,
> >
> > > Hi Rick,
> > >
> > > On Mon, May 10, 2021 at 3:22 PM Rick Chen wrote:
> > > >
> > > > Hi Bin
> > > >
> > &g
> 1 file changed, 11 insertions(+), 10 deletions(-)
Reviewed-by: Rick Chen
HI Bin,
>
> > Hi Rick,
> >
> > On Tue, May 11, 2021 at 8:49 AM Rick Chen wrote:
> > >
> > > Hi Bin,
> > >
> > > > Hi Rick,
> > > >
> > > > On Mon, May 10, 2021 at 3:22 PM Rick Chen wrote:
> > >
nfigs/ae350_rv64_spl_xip_defconfig | 2 ++
> 7 files changed, 13 insertions(+)
Reviewed-by: Rick Chen
Bin Meng
> Reviewed-by: Simon Glass
> ---
>
> (no changes since v1)
>
> common/Kconfig.boot | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
> Signed-off-by: Bin Meng
> Reviewed-by: Simon Glass
> ---
>
> (no changes since v1)
>
> tools/binman/binman.rst | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
+++
> tools/binman/etype/opensbi.py | 23 +++
> tools/binman/ftest.py | 7 +++
> tools/binman/test/201_opensbi.dts | 14 ++
> 4 files changed, 57 insertions(+)
Reviewed-by: Rick Chen
gt; Signed-off-by: Bin Meng
> ---
>
> doc/board/AndesTech/ax25-ae350.rst | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
> From: Bin Meng
> Sent: Friday, May 14, 2021 11:50 AM
> To: Green Wan
> Cc: Rick Jian-Zhi Chen(陳建志) ; Sean Anderson
> ; U-Boot Mailing List
> Subject: Re: [PATCH] Revert "riscv: cpu: fu740: clear feature disable CSR"
>
> On Fri, May 14, 2021 at 11:45 AM Green Wan wrote:
> >
> > Hi Bin,
> >
>
Hi Bin
> Hi Rick,
>
> On Wed, May 12, 2021 at 11:25 AM Rick Chen wrote:
> >
> > HI Bin,
> >
> > >
> > > > Hi Rick,
> > > >
> > > > On Tue, May 11, 2021 at 8:49 AM Rick Chen wrote:
> > > > >
> > > &g
-
> arch/riscv/cpu/fu540/Kconfig | 2 +-
> arch/riscv/cpu/generic/Kconfig | 3 ++-
> arch/riscv/include/asm/global_data.h | 2 +-
> arch/riscv/lib/Makefile | 2 +-
> drivers/timer/Makefile | 2 +-
> 6 files changed, 14 insertions(+), 6 deletions(-)
Reviewed-by: Rick Chen
rdt
> Reviewed-by: Bin Meng
> ---
> v2:
> fix typo in commit message
> ---
> common/board_f.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Rick Chen
s in ax25-ae350.h, while actually it
> is not. Remove it.
>
> Signed-off-by: Bin Meng
> ---
>
> doc/board/AndesTech/ax25-ae350.rst | 19 ---
> 1 file changed, 4 insertions(+), 15 deletions(-)
Reviewed-by: Rick Chen
in bootargs. Drop one.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 +-
> arch/riscv/dts/ae350_64.dts | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Rick Chen
Hi Bin,
> From: Bin Meng
> Sent: Friday, June 04, 2021 1:51 PM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; U-Boot Mailing List
> Subject: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL
> config
>
> At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. Th
HI Bin
> Hi Rick,
>
> On Wed, Jun 9, 2021 at 3:06 PM Rick Chen wrote:
> >
> > Hi Bin,
> >
> > > From: Bin Meng
> > > Sent: Friday, June 04, 2021 1:51 PM
> > > To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> > > ; U-Boot
g on Andes hardware, which I don't have access to.
> >
> > arch/riscv/lib/andes_plic.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
>
> Ping?
Though there will be only one hart will jump to U-Boot proper currently,
and this delay loop seem to be unnecessary.
But it is still a good catch.
Thanks,
Rick
Tested-by: Rick Chen
Reviewed-by: Rick Chen
> Hi Rick,
>
> On Sat, Jun 12, 2021 at 9:30 PM Rick Chen wrote:
> >
> > HI Bin
> >
> > > Hi Rick,
> > >
> > > On Wed, Jun 9, 2021 at 3:06 PM Rick Chen wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > &
gt; Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 ++
> arch/riscv/dts/ae350_64.dts | 2 ++
> 2 files changed, 4 insertions(+)
Reviewed-by: Rick Chen
des, so #address-cells is not needed.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 --
> arch/riscv/dts/ae350_64.dts | 2 --
> 2 files changed, 4 deletions(-)
Reviewed-by: Rick Chen
ir interrupt parent have 2
> cells encoded in their interrupts property, but plic0 only provides 1 cell in
> #interrupt-cells which is incorrect.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen
ch Schuchardt
> ---
> arch/riscv/lib/fdt_fixup.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
Reviewed-by: Rick Chen
This patch conflicts with Atish's [PATCH v3 0/2] Assorted fixes
related to reserved memory
Can you rebase it and send again ?
Thanks,
Rick
>
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Thursday, July 02, 2020 9:53 PM
> To: Open Source Project uboot
> Cc: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: [U-Boot] Pull request: u-boot-riscv/master
>
> On Thu, Jul 02, 2020 at 10:51:48AM +0800, ub...@andestech.com wrote:
Hi Jagan
> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> Sent: Thursday, July 02, 2020 4:03 PM
> To: Rick Jian-Zhi Chen(陳建志); Atish Patra; Palmer Dabbelt; Bin Meng; Paul
> Walmsley; Anup Patel; Sagar Kadam
> Cc: u-boot@lists.denx.de; linux-amar...@amarulasolutions.com; Jagan Teki; Bin
>
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Thursday, July 16, 2020 9:36 AM
> To: Sean Anderson
> Cc: Rick Jian-Zhi Chen(陳建志); Tom Rini; U-Boot Mailing List; Bin Meng
> Subject: Re: [PATCH 1/2] Revert "riscv: Allow use of reset drivers"
>
> Hi Rick,
>
> On Wed, Jul 8, 2020 at 3:04
Hi Bin
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Tom Rini
> Sent: Tuesday, July 07, 2020 10:13 PM
> To: Bin Meng
> Cc: U-Boot Mailing List; Bin Meng
> Subject: Re: [PATCH] azure: gitlab: travis: Update OpenSBI used for RISC-V
> testing
>
> On Sat, Jun 27, 2020 at 05:21:04A
for
> offset and mask property
>
> Hi Rick,
>
> On Fri, Jun 26, 2020 at 1:53 PM Pragnesh Patel
> wrote:
> >
> > >-Original Message-
> > >From: Bin Meng
> > >Sent: 23 June 2020 11:00
> > >To: Rick Chen ; Simon Glass ;
> >
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Monday, July 20, 2020 10:41 AM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Tom Rini; Bin Meng
> Subject: Re: [PATCH v2] azure: gitlab: travis: Update OpenSBI used for RISC-V
> testing
>
> Hi Rick,
>
> On Thu, Jul 16, 2020 at
Hi Bin
> Hi Rick,
>
> On Mon, Jul 20, 2020 at 11:16 AM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > Sent: Monday, July 20, 2020 10:41 AM
> > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
>
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Monday, July 20, 2020 11:52 AM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Tom Rini; Bin Meng
> Subject: [PATCH v3] azure: gitlab: travis: Update OpenSBI used for RISC-V
> testing
>
> From: Bin Meng
>
> Change to use OpenSBI releas
Hi Pragnesh
> Hi Rick,
>
> Any comments on this patch ?
Applied to u-boot-riscv/master !
Thanks,
Rick
> >From: U-Boot On Behalf Of Pragnesh Patel
> >Sent: 24 June 2020 13:14
> >To: Bin Meng ; Rick Chen
> >Cc: U-Boot Mailing List ; Atish Patra
> >;
Hi Sean
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Sean Anderson
> Sent: Tuesday, February 11, 2020 2:04 PM
> To: u-boot@lists.denx.de
> Cc: Rick Chen; Eugeniy Paltsev
> Subject: [PATCH v4 06/17] spi: dw: Add device tree properties for fields in
> CTRL
Hi Sean
This patch is relative about clock driver.
It shall be named as clk instead of riscv
Thanks
Rick
> This is a small driver to do a software bypass of a clock if hardware
> bypass is not working. I have tried to write this in a generic fashion, so
> that it could be potentially broken out o
Hi Sean
> On 2/18/20 1:35 AM, Rick Chen wrote:
> > Hi Sean
> >
> > This patch is relative about clock driver.
> > It shall be named as clk instead of riscv
> > Thanks
> > Rick
>
> Should the other clock patches adding k210 clock support be prefixed
>
Hi Sean
> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> just enable them as normal. The enable count is local to the struct clk,
> but this will never result in the actual en-/dis-able op being called
> (unless the same struct clk is enabled twice).
>
> For clocks in t
Hi Sean
> The dw spi devices on the Kendryte K210 must be operated in a specific
> fasion which cannot be achived through multiple writes to via dw_spi_xfer
> (as it is currently written). This patch adds an implementation of exec_op,
> which gives correct behaviour when reading/writing spi flash.
Hi Sean
> >> The dw spi devices on the Kendryte K210 must be operated in a specific
> >> fasion which cannot be achived through multiple writes to via dw_spi_xfer
> >> (as it is currently written). This patch adds an implementation of exec_op,
> >> which gives correct behaviour when reading/writin
Hi Sean
> On 2/18/20 2:20 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> >> just enable them as normal. The enable count is local to the struct clk,
> >> but this will never result
Hi Sean
> The IPI code could have race conditions in several places.
> * Several harts could race on the value of gd->arch->clint/plic
> * Non-boot harts could race with the main hart on the DM subsystem In
> addition, if an IPI was pending when U-Boot started, it would cause the
> IPI handler
Hi Sean
> This header is needed outside of the arm architecture for the designware
> watchdog.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Simon Glass
> ---
> This patch previously appeared as
> https://patchwork.ozlabs.org/patch/1232411/
>
> Changes in v5:
> - New
I wonder why this is ARM
Hi Sean
> On Mon, 2020-03-02 at 10:43 -0500, Sean Anderson wrote:
>
> > On 3/2/20 4:08 AM, Rick Chen wrote:
> > > Hi Sean
> > >
> > > > The IPI code could have race conditions in several places.
> > > > * Several harts could race on the value
Hi Sean
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a
> "KPU" neural network processor, an audio processor supporting
Hi Sean
> Some devices have different layouts for the fields in CTRL1 (e.g. the
Still not fix this typo in commit message
CTRL1 -> CTRL0
Thanks,
Rick
> Kendryte K210). Allow this layout to be configurable from the device tree.
> The documentation has been taken from Linux.
>
> Signed-off-by: S
Hi Sean
> Some older processors (notably the Kendryte K210) use an older version of
> the RISC-V privileged specification. The primary changes between the old
> and new are in virtual memory, and in the merging of three separate counter
> enable CSRs. Using the new CSR on an old processor causes
Hi Sean
> The Fully-Programmable Input/Output Array (FPIOA) device controls pin
> multiplexing on the K210. The FPIOA can remap any supported function to any
> multifunctional IO pin. It can also perform basic GPIO functions, such as
> reading the current value of a pin.
>
> Signed-off-by: Sean An
Hi Sean
> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> just enable them as normal. The enable count is local to the struct clk,
> but this will never result in the actual en-/dis-able op being called
> (unless the same struct clk is enabled twice).
>
> For clocks in t
Hi Sean
> Due to the large number of clocks, I decided to use the CCF. The overall
> structure is modeled after the imx code. Clocks are stored in several
> arrays. There are some translation macros (FOOIFY()) which allow for more
> dense packing. A possible improvement could be to only store th
Hi Sean
This patch series become larger and larger from v1 with 11 patches to
v5 with 33 patches.
You shall just fix the suggestions from the previous version in the
next version.
Additional extra features and subsystem drivers that you want to
support, you shall send them individually instead of
");
> + return -1;
> + }
> + chosen_offset = fdt_path_offset(blob, "/chosen");
> + fdt_setprop_u32(blob, chosen_offset, "boot-hartid",
> + gd->arch.boot_hart);
Is it also OK for RV64 ?
Other than that,
Reviewed-by: Rick Chen
> +
> return 0;
> }
>
> --
> 2.24.0
>
Hi Sean
> Hi Sean
>
> > On Mon, 2020-03-02 at 10:43 -0500, Sean Anderson wrote:
> >
> > > On 3/2/20 4:08 AM, Rick Chen wrote:
> > > > Hi Sean
> > > >
> > > > > The IPI code could have race conditions in several places.
> &g
Hi Sean
> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> just enable them as normal. The enable count is local to the struct clk,
> but this will never result in the actual en-/dis-able op being called
> (unless the same struct clk is enabled twice).
>
> For clocks in t
Hi Bin
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, March 10, 2020 9:54 AM
> To: Lukas Auer; Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Subject: Re: [PATCH 1/2] riscv: Fix sbi_remote_sfence_vma{,_asid}
>
> Hi Rick,
>
> On Fri, Mar 6, 2020 at 4:44 PM Bin Meng wrote:
> >
> > Cu
Hi Sean
> > For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> > just enable them as normal. The enable count is local to the struct clk,
> > but this will never result in the actual en-/dis-able op being called
> > (unless the same struct clk is enabled twice).
> >
> > For
Hi Sean
> This patch adds alternate versions of the clk_*_register functions for use
> with statically-allocated struct clks. This allows drivers to define clocks
> at compile-time and register them at run-time without malloc-ing. This
> increases the size of the binary, but should not affect ram
Hi Sean
> The IPI code could have race conditions in several places.
> * Several harts could race on the value of gd->arch->clint/plic
> * Non-boot harts could race with the main hart on the DM subsystem In
> addition, if an IPI was pending when U-Boot started, it would cause the
> IPI handler
Hi Sean
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a
> "KPU" neural network processor, an audio processor supporting
Hi Sean
> Where possible, I have tried to find compatible drivers based on the layout
> of registers. However, many devices remain untested. All untested devices
> have been left disabled, but some tentative properties (such as compatible
> strings, and clocks, interrupts, and resets properties) h
Hi Sean
> On 3/10/20 4:20 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> The IPI code could have race conditions in several places.
> >> * Several harts could race on the value of gd->arch->clint/plic
> >> * Non-boot harts could race with the main hart o
Hi Sean
> On 3/10/20 5:08 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> Where possible, I have tried to find compatible drivers based on the layout
> >> of registers. However, many devices remain untested. All untested devices
> >> have been left disabl
Hi Sean
> On 3/10/20 5:04 AM, Rick Chen wrote:
> > Hi Sean
> >
> >> The Sipeed Maix series is a collection of boards built around the RISC-V
> >> Kendryte K210 processor. This processor contains several peripherals to
> >> accelerate neural network proces
Hi Sean
> On 3/10/20 2:51 AM, Rick Chen wrote:
> > Hi Sean
> >
> >>> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> >>> just enable them as normal. The enable count is local to the struct clk,
> >>> but this will neve
have Kconfig entries that set SPL_LDSCRIPT to what is the
> default value anyways. Drop these.
>
> Cc: Michal Simek
> Cc: Rick Chen
> Cc: Philippe Reynes
> Cc: Eric Jarrige
> Signed-off-by: Tom Rini
> ---
> arch/microblaze/Kconfig | 3 ---
> arch/risc
Hi Bin
>
> Hi Rick,
>
> On Wed, Oct 30, 2019 at 8:42 AM Rick Chen wrote:
> >
> > Hi Bin
> >
> > >
> > > Hi Rick,
> > >
> > > On Fri, Oct 25, 2019 at 2:17 PM Andes wrote:
> > > >
> > > > From: Rick Che
Hi Bin
>
> Hi Rick,
>
> On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> >
> > Hi Bin
> >
> > >
> > > Hi Rick,
> > >
> > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > >
> > > > From: R
Hi Bin
>
> Hi Rick,
>
> On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > The mcache_ctl csr only can be manipulated in M mode.
> > Add SPL_RISCV_MMODE for U-Boot SPL to control cache
> > operation.
> >
> >
Hi Bin
>
> Hi Rick,
>
> On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > When ax25-ae350 try to enable v5l2 cache
> > driver in SPL configuration, it need this
> > option for cache support in SPL.
> >
> >
Hi Bin
>
> Hi Rick,
>
> On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > For RV64, it will use sd instruction to clear t0
> > register, and the increament will be 8 bytes. So
> > if the difference between__bss_stra
Hi Bin
Bin Meng 於 2019年10月31日 週四 上午11:02寫道：
>
> Hi Rick,
>
> On Thu, Oct 31, 2019 at 10:53 AM Rick Chen wrote:
> >
> > Hi Bin
> >
> > >
> > > Hi Rick,
> > >
> > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > &g
Hi Bin
>
> Hi Rick,
>
> On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > Add CPU2 and CPU3 informations in cpus node
>
> nits: information
OK
>
> > to support four cores SMP booting.
> >
>
Hi Bin
>
> Hi Rick,
>
> On Thu, Oct 31, 2019 at 11:10 AM Rick Chen wrote:
> >
> > Hi Bin
> >
> > >
> > > Hi Rick,
> > >
> > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > >
> > > > From: Rick Chen
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