On 2/21/23 08:03, Ashok Reddy Soma wrote:
From: Algapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'board_boot_order' [-Wmissing-prototypes].
Signed-off-by: Algapally Santosh Sagar
Signed-off-by: Ashok Reddy Soma
---
arch/arm/mac
On 2/22/23 02:06, Marek Vasut wrote:
On 1/13/23 06:12, Venkatesh Yadav Abbarapu wrote:
As the "reset-gpios" property is optional, don't return the
error and just skip the gpio reset sequence.
Signed-off-by: Venkatesh Yadav Abbarapu
---
Changes in v2:
- Replaced the gpio_request_by_name() th
On 2/22/23 16:33, Marek Vasut wrote:
On 2/22/23 08:01, Michal Simek wrote:
On 2/22/23 02:06, Marek Vasut wrote:
On 1/13/23 06:12, Venkatesh Yadav Abbarapu wrote:
As the "reset-gpios" property is optional, don't return the
error and just skip the gpio reset sequence.
Hi,
On 2/24/23 05:53, Ashok Reddy Soma wrote:
From: Algapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'board_boot_order' [-Wmissing-prototypes].
Signed-off-by: Algapally Santosh Sagar
Signed-off-by: Ashok Reddy Soma
---
Changes in
On 2/15/23 09:45, Michal Simek wrote:
Printing return value in HEX instead of DEC. Return values are 64 bit
values which impossible to decode in DEC. For example getting CHIP ID in
dec is quite long.
Signed-off-by: Michal Simek
---
cmd/smccc.c | 2 +-
1 file changed, 1 insertion(+), 1
On 2/20/23 09:09, Michal Simek wrote:
The latest SOM specification doesn't enforce certain MIO lines allocated
for ethernet or ethernet controller itself. That's why remove comment about
it which is likely there from early version of specification.
Also removed the same comment fr
On 2/21/23 06:22, Jiajie Chen wrote:
It was incorrectly using an old priv->regs pointer, and may lead to null
pointer access.
I would describe it a little bit differently to describe what it happening.
priv structure is initiated by DM core to zeros that's why regs property is
pointing to
On 2/27/23 15:58, Dario Binacchi wrote:
Hi Ashok,
On Fri, Feb 24, 2023 at 6:07 AM Ashok Reddy Soma
wrote:
DC3 nand node is not correct, it is showing all partitions under
controller node directly. Create two sub nand nodes with partitions for
each.
Signed-off-by: Ashok Reddy Soma
---
On 2/28/23 01:52, jassisinghb...@gmail.com wrote:
From: Jassi Brar
Any requirement of FWU should not require changes to bindings
of other subsystems. For example, for mtd-backed storage we
can do without requiring 'fixed-partitions' children to also
carry 'uuid', a property which is non-stan
;
>
> + regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
> priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
>
> writel(SPISSR_RESET_VALUE, ®s->srr);
> --
> 2.30.2
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), Ope
On 2/24/23 06:07, Ashok Reddy Soma wrote:
In this patch series
- Remove hardcoding of NAND_BBT_USE_FLASH in nand->bbt_options
- Find and update nand ofnode.
- Fix nand node in zynqmp-zc1751-xm017-dc3.dts file
- Enable nand-on-flash-bbt flag in zynqmp DT's by default
Ashok Reddy Soma
Hi,
On 3/7/23 15:02, Michael Nazzareno Trimarchi wrote:
Hi
On Tue, Mar 7, 2023 at 2:35 PM Michal Simek <mailto:michal.si...@amd.com>> wrote:
On 2/24/23 06:07, Ashok Reddy Soma wrote:
> In this patch series
> - Remove hardcoding of NAND_BBT_USE_FLASH in na
On 3/1/23 11:33, Ashok Reddy Soma wrote:
Run and fix sparse warnings in below files
-arch/arm/mach-zynqmp/include/mach/sys_proto.h
-common/spl/spl.c
-arch/arm/mach-versal-net/include/mach/sys_proto.h
-arch/arm/mach-versal/include/mach/sys_proto.h
-drivers/mmc/zynq_sdhci.c
-drivers/
On 3/5/23 18:49, Ovidiu Panait wrote:
Add elf16_to_cpu() and elf32_to_cpu() functions that allow to read data in
both big-endian and little-endian formats.
Signed-off-by: Ovidiu Panait
---
tools/relocate-rela.c | 20
1 file changed, 20 insertions(+)
diff --git a/too
offset = le32_to_cpu(sh_table[i].sh_offset);
+ sh_size = le32_to_cpu(sh_table[i].sh_size);
if (!strcmp(".rela.dyn", sh_name)) {
debug("Found section\t\".rela_dyn\"\n");
Reviewed-by: Michal Simek
Thanks,
Michal
swrela.r_offset = elf32_to_cpu(rela.r_offset);
+ swrela.r_info = elf32_to_cpu(rela.r_info);
+ swrela.r_addend = elf32_to_cpu(rela.r_addend);
debug("SWRela:\toffset:\t%" PRIx32 " r_info:\t%"
PRIu32 " r_addend:\t%" PRIx32 "\n",
Reviewed-by: Michal Simek
Thanks,
Michal
f !NEEDS_MANUAL_RELOC
+ def_bool y
choice
prompt "Target select"
Reviewed-by: Michal Simek
Thanks,
Michal
-#endif
/* Flush caches to ensure consistency */
brlid r15, flush_cache_all
Reviewed-by: Michal Simek
Thanks,
Michal
On 3/11/23 18:38, Ovidiu Panait wrote:
Add elf16_to_cpu() and elf32_to_cpu() functions that allow to read data in
both big-endian and little-endian formats.
Reviewed-by: Michal Simek
I didn't give you this line in v1.
But patch looks fine now.
Applied the whole series.
Thanks,
Michal
ies
Michael Grzeschik (1):
arm64: zynqmp: Enable hs termination flag for USB dwc3 controller
Michal Simek (6):
xilinx: dts: Remove cdns,zynq-gem
ARM: zynq: Use recommended dma-controller name instead of dmac
ARM: zynq: Comment interrupt names IRQs for pl330
cmd: sm
Hi,
On 3/16/23 17:52, Stefan Herbrechtsmeier wrote:
Hi Siva Durga Prasad Paladugu,
we want to add rgmii-id support to the gmiitorgmii phy driver. How does the
correct device tree for the gmiitorgmii looks like? The converter sits between
the MAC and the external PHY (MAC <==> GMII2RGMII <==>
On 3/21/23 13:58, Patrick Delaunay wrote:
Remove test on CONFIG_LMB_MEMORY_REGIONS introduced by commit
7c1860fce4e3 ("lmb: Fix lmb property's defination under struct lmb").
This code in lmb_init() is strange, because if CONFIG_LMB_USE_MAX_REGIONS
and CONFIG_LMB_MEMORY_REGIONS are not defined
Alex Nemirovsky
Cc: Haolin Li
Cc: Heinrich Schuchardt
Cc: Joe Hershberger
Cc: Joel Stanley
Cc: Josua Mayer
Cc: Marek Vasut
Cc: Michael Trimarchi
Cc: Michal Simek
Cc: Nate Drude
Cc: Neil Armstrong
Cc: Radu Pirea
Cc: Ramon Fried
Cc: Samuel Mendoza-Jonas
Cc: Stefan Roese
Cc: T Karthik
Hi Simon and Tom,
On 3/14/23 09:46, Venkatesh Yadav Abbarapu wrote:
From: Algapally Santosh Sagar
The baudrate configured in .config is taken by default by serial. If
change of baudrate is required then the .config needs to changed and
u-boot recompilation is required or the u-boot environment
On 3/20/23 16:55, Stefan Herbrechtsmeier wrote:
From: Stefan Herbrechtsmeier
Read the phy mode of the external phy from the device tree if available.
Signed-off-by: Stefan Herbrechtsmeier
---
drivers/net/phy/xilinx_gmii2rgmii.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
cfi_mtd requires add_mtd_device() which is available only when MTD is
enabled that's why record this dependency.
Signed-off-by: Michal Simek
---
drivers/mtd/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 5fa88da
ed reference to `gpio_request_by_name'
Signed-off-by: Michal Simek
---
drivers/sysreset/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 03f7fdd59785..bdbe2a95364d 100644
--- a/drivers/sysreset/Kconfig
+++ b/driv
Grrr. Patch subject prefix should be fixed.
The rest looks good to me.
M
On 7/7/23 08:59, Ashok Reddy Soma wrote:
When CONFIG_CMD_MMC and CONFIG_MMC are disabled, still some compilation
errors are seen as below due to unresolved symbols.
drivers/dfu/dfu_mmc.o: in function `mmc_block_op':
dr
pá 23. 6. 2023 v 14:52 odesílatel Michal Simek napsal:
>
> zynqmp_mmio_read/write() are firmware provided hooks that's why use only
> zynqmp_firmware.h for function declaration.
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/mach-versal-net/include/mach/sys_pr
On 6/27/23 11:04, christian.taedcke-...@weidmueller.com wrote:
From: Christian Taedcke
This way custom logic can be implemented per board after the fpga
image is uploaded.
What do you want to do there?
I expect Simon won't like that it is another weak function.
Signed-off-by: Christian
/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -3,8 +3,7 @@
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek
-obj-y += clk.o
-obj-y += cpu.o
+obj-y += aes.o clk.o cpu.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj
From: Raju Kumar Pothuraju
Enables the FDT library (libfdt) overlay support for zynq platforms
to be able to use fdt apply command.
Signed-off-by: Raju Kumar Pothuraju
Signed-off-by: Michal Simek
---
configs/xilinx_zynq_virt_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a
: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
drivers/mmc/zynq_sdhci.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index e779251ce34f..935540d17194 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc
Update my and DPs email address to match current setup.
Signed-off-by: Michal Simek
---
The same changes have been done in Linux.
Link:
https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.si...@amd.com
---
arch/arm/dts/avnet-ultra96-rev1.dts | 2
: Increase reset assert time for TI SGMII PHY
arm64: zynqmp: Assign TSU clock frequency for KV and KD boards
Manikanta Guntupalli (1):
xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
Michal Simek (8):
arm64: zynqmp: Fix gpio comment about No of gpios
arm64: zynqmp: Record compatible
From: Varalaxmi Bingi
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of
400kHz. Current default value is 100kHz.
Signed-off-by: Varalaxmi Bingi
Signed-off-by: Michal Simek
---
arch/arm/dts/zynq-7000.dtsi | 2 ++
arch/arm/dts/zynqmp.dtsi| 2 ++
2 files changed, 4
-send-email-parth.gaj...@amd.com
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 2 +-
arch/arm/dts/zynqmp.dtsi | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 173e4bc5f1d8
From: Manikanta Guntupalli
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by
Linux.
"enforced open drain please flag it properly in DT/ACPI DSDT/board
file."
Signed-off-by: Manikanta Guntupalli
Signed-off-by: Michal Simek
---
arch/arm/dts/zynq
From: Harini Katakam
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KR260 CC to allow PTP functionality.
Signed-off-by: Harini Katakam
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 4
arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 ++
arch/arm
There are total 174 gpios but from 0 - 173 that's why fix comment to
reflect it.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +-
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +-
arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +-
arch/arm/dts/zynqmp-m-a21
: Michal Simek
---
arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +-
arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index caaf71d729e4..d318773bd9d6 100644
--- a
From: Harini Katakam
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KV and KD carrier cards to allow PTP functionality.
Signed-off-by: Harini Katakam
Reviewed-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 1 +
arch/arm
PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335
autofocus feature). PS side is completely unchanged.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-sck-kv-g
Extend compatible versions for K24 SOM.
Changes are not affecting SW behavior that's why all versions are
compatible to each other.
Describing all revisions is done by purpose because user space SW is
reading compatible string for logic around DT overlays and bitstreams.
Signed-off-by: M
sb5744
hub which is used only in host mode. Especially this chip requires reset to
operate properly that's why better assign gpio reset to usb1 instead of
usb0.
Without this change usb start crashed when runs.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zcu100-revC.dts | 2 ++
1
From: Radhey Shyam Pandey
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.
Reported-by: John Toomey
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Mi
Address in node name should match with the first reg property in DT.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 59b52919f130..b9cfd562c913 100644
--- a
-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b9cfd562c913..11eaf4b6a193 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -149,6 +149,10
off-by: Piyush Mehta
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 11eaf4b6a193..223cdab5f93d 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.d
These two properties are not described in DT binding and also not used by
driver that's why remove them.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 223cdab
Fix child node names to be aligned with dt-binding available in the Linux
kernel which requires names as ams-ps@ and ams-pl@.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts
Clock is not used in driver and also not described in binding.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 4
arch/arm/dts/zynqmp.dtsi | 1 -
2 files changed, 5 deletions(-)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
Hi,
On 7/11/23 07:00, Jaehoon Chung wrote:
Hi,
-Original Message-
From: Michal Simek
Sent: Monday, July 10, 2023 9:12 PM
To: u-boot@lists.denx.de; g...@xilinx.com
Cc: Ashok Reddy Soma ; Jaehoon Chung
; Peng Fan
Subject: [PATCH] mmc: zynq_sdhci: Dll reset only for ZynqMP platform
On 7/10/23 17:50, Marek Vasut wrote:
On 7/10/23 17:47, Simon Glass wrote:
Hi,
On Mon, 10 Jul 2023 at 09:15, Taedcke, Christian
wrote:
Am 10.07.2023 um 15:44 schrieb Marek Vasut:
On 7/10/23 15:02, Taedcke, Christian wrote:
Am 10.07.2023 um 13:41 schrieb Michal Simek:
On 6/27/23 11
s://lwn.net/Articles/848265/
I think you can rename incorrect tag first and remove origin one.
And creating new tag (with -rc6 removed from Makefile) make sense to me.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer o
Hi Sean,
On 7/11/23 15:40, Sean Anderson wrote:
On 7/11/23 05:51, Ashok Reddy Soma wrote:
There is a chance that assigned-clock-rates is given and assigned-clocks
could be empty. Dont return error in that case, because the probe of the
corresponding driver will not be called at all if this fail
On 7/11/23 16:28, Sean Anderson wrote:
On 7/11/23 10:20, Michal Simek wrote:
Hi Sean,
On 7/11/23 15:40, Sean Anderson wrote:
On 7/11/23 05:51, Ashok Reddy Soma wrote:
There is a chance that assigned-clock-rates is given and assigned-clocks
could be empty. Dont return error in that case
Santosh Sagar
Signed-off-by: Michal Simek
---
Changes in v2:
- s/bootscr-offset-from-ram-start/bootscr-ram-offset/
- Aligned with https://github.com/devicetree-org/dt-schema/pull/105
board/xilinx/common/board.c | 43 ++---
1 file changed, 40 insertions(+), 3
s that from new flashed image stable image can be
rewritten because in_trial is not setup properly.
Signed-off-by: Michal Simek
---
lib/fwu_updates/fwu.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c
index cd5c3b64773b..38b50cb7628c 1
Empty capsule are also allowed to be process. Without it updated images
can't change their Image Acceptance state from no to yes.
Signed-off-by: Michal Simek
---
lib/efi_loader/efi_capsule.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_capsul
o: 'mtd nor0=bank0 raw 232 8;bank1 raw 27a
8&mtd nor0=bank0 raw 23a 400;bank1 raw 282 400'
Size for bank0 and bank1 must be the same because it is the same image.
Signed-off-by: Michal Simek
---
lib/fwu_updates/fwu_mtd.c | 6 --
1 file chang
On 7/13/23 22:51, Simon Glass wrote:
Hi Michal,
On Thu, 13 Jul 2023 at 06:54, Michal Simek wrote:
From: Algapally Santosh Sagar
The bootscript is expected at a default address specific to each
platform.
When high speed memory like Programmable Logic Double Data Rate RAM
(PL DDR RAM) or
It is not visible anywhere in Trial State if this is the first, second, etc
attempt that's why show a message to be aware about status.
Signed-off-by: Michal Simek
---
lib/fwu_updates/fwu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/
On 6/24/23 15:41, Sughosh Ganu wrote:
Add support for specifying the parameters needed for capsule
generation through a config file, instead of passing them through
command-line. Parameters for more than a single capsule file can be
specified, resulting in generation of multiple capsules throu
On 7/15/23 14:30, Sughosh Ganu wrote:
On Fri, 14 Jul 2023 at 16:14, Michal Simek wrote:
On 6/24/23 15:41, Sughosh Ganu wrote:
Add support for specifying the parameters needed for capsule
generation through a config file, instead of passing them through
command-line. Parameters for more
ions(+), 2 deletions(-)
diff --git a/.mailmap b/.mailmap
index 312a428dc9f6..05cb310e416f 100644
--- a/.mailmap
+++ b/.mailmap
@@ -65,8 +65,8 @@ Marek Vasut
Marek Vasut
Marek Vasut
Markus Klotzbuecher
-Masahiro Yamada
-Masahiro Yamada
+Masahiro Yamada
+Masahiro Yamada
Michal Simek
On 7/10/23 13:56, Michal Simek wrote:
From: Raju Kumar Pothuraju
Enables the FDT library (libfdt) overlay support for zynq platforms
to be able to use fdt apply command.
Signed-off-by: Raju Kumar Pothuraju
Signed-off-by: Michal Simek
---
configs/xilinx_zynq_virt_defconfig | 1 +
1
On 7/10/23 14:35, Michal Simek wrote:
Update my and DPs email address to match current setup.
Signed-off-by: Michal Simek
---
The same changes have been done in Linux.
Link:
https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.si...@amd.com
---
arch
/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index bb1830c846..1a76493bef 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -3,8 +3,7 @@
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek
-obj-y += clk.o
-obj-y += cpu.o
+obj-y += aes.o clk.o
On 6/26/23 05:32, Venkatesh Yadav Abbarapu wrote:
Add support for Winbond 256M-bit flash w25q256jwm.
Performed basic erase/write/readback operations on
ZynqMP zc1751+dc1 board.
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-ids.c | 5 +
1 file changed, 5 insertion
On 7/10/23 14:11, Michal Simek wrote:
From: Ashok Reddy Soma
Dll reset is needed only for ZynqMP platforms, add condition in tuning
to call arasan_zynqmp_dll_reset() just for ZynqMP platforms.
On other platforms like Versal NET, If this condition is not added, we
see PLM error messages
On 7/4/23 14:04, Michal Simek wrote:
cfi_mtd requires add_mtd_device() which is available only when MTD is
enabled that's why record this dependency.
Signed-off-by: Michal Simek
---
drivers/mtd/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver
On 7/10/23 14:37, Michal Simek wrote:
sending couple of DT patches to be in sync with Linux repository.
There are still some changes but we are working on it to get them fully in
sync for SystemReady IR certification.
Thanks,
Michal
Harini Katakam (3):
arm64: zynqmp: Assign TSU clock
e[2]: *** [scripts/Makefile.build:257: board/keymile/kmcent2/kmcent2.o]
Error 1
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal
On 7/4/23 08:16, Ashok Reddy Soma wrote:
When CONFIG_SYS_REDUNDAND_ENVIRONMENT is enabled, by default env is
getting saved to redundant environment irrespective of primary env is
present or not.
It means even if primary and redundant environment are not present, by
default, env is getting sto
On 7/18/23 17:41, Heinrich Schuchardt wrote:
On 13.07.23 16:35, Michal Simek wrote:
Empty capsule are also allowed to be process. Without it updated images
can't change their Image Acceptance state from no to yes.
Is there any documentation describing the usage of empty capsule to se
On 7/18/23 13:22, Taedcke, Christian wrote:
Hello Michal,
On 17.07.2023 12:36, Michal Simek wrote:
On 7/12/23 13:39, christian.taedcke-...@weidmueller.com wrote:
From: Christian Taedcke
This enables implementing custom logic after a bitstream was loaded
into the fpga.
Signed-off-by
On 7/19/23 08:53, Maksim Kiselev wrote:
If there is no incoming package than axiemac_recv will return -1 which
in turn leads to printing `eth_rx: recv() returned error -1` error
message in eth_rx function. But missing a package is not an fatal error,
so return -EAGAIN in that case would be mor
Hi,
On 7/20/23 07:49, AKASHI Takahiro wrote:
Hi,
On Wed, Jul 19, 2023 at 08:28:41AM +0200, Michal Simek wrote:
On 7/18/23 17:41, Heinrich Schuchardt wrote:
On 13.07.23 16:35, Michal Simek wrote:
Empty capsule are also allowed to be process. Without it updated images
can't change
On 7/20/23 08:36, Sughosh Ganu wrote:
On Thu, 20 Jul 2023 at 11:37, Michal Simek wrote:
Hi,
On 7/20/23 07:49, AKASHI Takahiro wrote:
Hi,
On Wed, Jul 19, 2023 at 08:28:41AM +0200, Michal Simek wrote:
On 7/18/23 17:41, Heinrich Schuchardt wrote:
On 13.07.23 16:35, Michal Simek wrote
On 7/20/23 10:45, Sughosh Ganu wrote:
On Thu, 20 Jul 2023 at 13:26, Michal Simek wrote:
On 7/20/23 08:36, Sughosh Ganu wrote:
On Thu, 20 Jul 2023 at 11:37, Michal Simek wrote:
Hi,
On 7/20/23 07:49, AKASHI Takahiro wrote:
Hi,
On Wed, Jul 19, 2023 at 08:28:41AM +0200, Michal Simek
Hi Sean,
On 7/11/23 16:55, Michal Simek wrote:
On 7/11/23 16:28, Sean Anderson wrote:
On 7/11/23 10:20, Michal Simek wrote:
Hi Sean,
On 7/11/23 15:40, Sean Anderson wrote:
On 7/11/23 05:51, Ashok Reddy Soma wrote:
There is a chance that assigned-clock-rates is given and assigned-clocks
On 7/19/23 10:49, Ashok Reddy Soma wrote:
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma
---
drivers/clk/clk_zynqmp.c | 2 ++
1 file changed, 2 insertions(+)
d
On 7/20/23 09:28, Ashok Reddy Soma wrote:
Add gem_tsu and gem0_rx till gem3_rx to return proper register from
zynqmp_clk_get_register. Otherwise firmware won't be able to set clock
for these due to incorrect register address.
Signed-off-by: Ashok Reddy Soma
---
drivers/clk/clk_zynqmp.c |
tupalli (1):
xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
Michal Simek (12):
watchdog: versal: Use new compatible xlnx,versal-wwdt
xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.h
arm64: zynqmp: Switch to amd.com emails
mtd: Add m
On 7/18/23 13:53, lukas.funke-...@weidmueller.com wrote:
From: Lukas Funke
Add the Xilinx Bootgen as bintool. Xilinx Bootgen is used to create
bootable SPL (FSBL in Xilinx terms) images for Zynq/ZynqMP devices. The
btool creates a signed version of the SPL. Additionally to signing the
key so
On 7/18/23 13:53, lukas.funke-...@weidmueller.com wrote:
From: Lukas Funke
This series adds two etypes to create a verified boot chain for
Xilinx ZynqMP devices. The first etype 'xilinx-fsbl-auth' is used to
create a bootable, signed image for ZynqMP boards using the Xilinx
Bootgen tool. Th
On 7/20/23 09:27, christian.taedcke-...@weidmueller.com wrote:
From: Christian Taedcke
This enables implementing custom logic after a bitstream was loaded
into the fpga.
Signed-off-by: Christian Taedcke
Reviewed-by: Simon Glass
---
Changes in v5:
- remove changes from kmcent2 board file
/mach/zynqmp_aes.h
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index bb1830c846..1a76493bef 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -3,8 +3,7 @@
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek
-obj-y += clk.o
fclk will never go upstream that's why removing this node from DT.
All PL (programmable logic) based IPs should handle clocks self without
using this workaround.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 6 --
1 file changed, 6 deletions(-)
diff --git a/arc
Hi,
I have found 5 more patches internally which should be also upstreamed to
get DT in sync and descrease amount of differences.
Thanks,
Michal
Michal Simek (4):
arm64: zynqmp: Use mdio node by vp-x-a2785-00-revA and vpk120-revA
arm64: zynqmp: Remove xlnx,zynqmp-aes node
Revert "
e.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 463ac14f4b59..366b50a104be 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -257,7 +257,6 @@
AES can be discovered via firmware interface that's why remove node for it.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index f03c201caee9..463ac14f4b59 100644
--- a/arc
All boards have been converted to use mdio node that's why move ethernet
phys under mdio node too.
Signed-off-by: Michal Simek
---
Same change was done by:
https://lore.kernel.org/r/ff165281a70a38e2b76fee91e6255ce95ce8021b.1695378830.git.michal.si...@amd.com
---
arch/arm/dts/zynqmp-vp-x-
From: Piyush Mehta
To sync up with the upstream bulk-stream feature, removed
'snps,xhci-stream-quirk' DT property for usb.
Signed-off-by: Piyush Mehta
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/dts/zyn
Remove unused address/size-cells which is also done upstream that's why
this is pretty much sync patch with upstream.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
From: Venkatesh Yadav Abbarapu
As mini configs are required only for flashing the images, so
disabling the lock config which will save nearly 6KB of memory.
Signed-off-by: Venkatesh Yadav Abbarapu
Signed-off-by: Michal Simek
---
Depends on
https://lore.kernel.org/all/20230928034940.2220-2
From: Venkatesh Yadav Abbarapu
Lock size for the flashes will be in terms of sector size, so
disable the CONFIG_SPI_FLASH_USE_4K_SECTORS and read it from the
flash itself.
Signed-off-by: Venkatesh Yadav Abbarapu
Signed-off-by: Michal Simek
---
configs/xilinx_zynq_virt_defconfig | 1 +
1
From: Amit Kumar Mahapatra
Except for Linux no other component (i.e., u-boot, fsbl or BootRom) of the
software stack supports software ecc engine. So, make hw-ecc as the default
ecc mode.
Signed-off-by: Amit Kumar Mahapatra
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1751-xm016
On 9/12/23 05:59, Venkatesh Yadav Abbarapu wrote:
The xhci host controller driver trying to queue the URB's and it is
getting halted at the endpoint, thereby hitting the BUG_ON's.
Mostly these kind of random issues are seen on faulty boards.
Removing these BUG_ON's from the U-Boot xhci code, a
1 - 100 of 8100 matches
Mail list logo
