Hi Pantelis,
> Hi Yangbo,
>
> > On Jun 24, 2015, at 05:13 , Yangbo Lu wrote:
> >
> > It needs to flush D-cache before 'mmc read' so that we can see the
> > right data in DDR. And fix parameter for invalidate_dcache_range()
> > after 'mmc read'.
> >
> > Signed-off-by: Yangbo Lu
> > Cc: York Sun
Hi York,
Please see my comments below.
> -Original Message-
> From: Sun York-R58495
> Sent: Monday, September 14, 2015 11:57 PM
> To: Lu Yangbo-B47093; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/3] mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5
>
> Yangbo,
>
> On 09/13/2015 08:04 PM, Yan
> On 09/14/2015 07:22 PM, Lu Yangbo-B47093 wrote:
> > Hi York,
> >
> > Please see my comments below.
> >
> >> -Original Message-
> >> From: Sun York-R58495
> >> Sent: Monday, September 14, 2015 11:57 PM
> >> To: Lu Yangbo-B47093; u-boot@lists.denx.de
> >> Subject: Re: [PATCH 1/3] mmc: fsl_e
Hello Hector,
I am not familiar with iMX6 based board.
I only know the DAT0 checking was introduced in commit
7a5b80297bc6cef0c10e5f57ac0450678dc7bc5e
And different cards may have different secure erase timeout value.
This should be found in chip datasheet.
But I've never meet your issue...
>
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