On Thu, Jan 19, 2023 at 03:05:39PM +0800, Yu Chien Peter Lin wrote:
> Update the compatible string of L2 cache.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/dts/ae350_32.dts | 2 +-
> arch/riscv/dts/ae350_64.dts | 2 +-
> drivers/cache/cache-v5l2.c | 2 +-
> 3 files changed, 3 inser
On Thu, Jan 19, 2023 at 03:05:40PM +0800, Yu Chien Peter Lin wrote:
> This patch refines L1 cache enable/disable and v5l2-cache enable
> functions.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/cpu/ax25/cache.c | 100
> 1 file changed, 68 insertion
On Thu, Jan 19, 2023 at 03:05:41PM +0800, Yu Chien Peter Lin wrote:
> Enable cache-v5l2 driver for each AE350 defconfig.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> configs/ae350_rv32_defconfig | 1 +
> configs/ae350_rv32_spl_defconfig | 3 +++
> configs/ae350_rv32_spl_xip_defconfi
On Thu, Jan 19, 2023 at 03:05:42PM +0800, Yu Chien Peter Lin wrote:
> Loading image over TFTP is often interrupted since it does more than
> 10 times retries, increase the number of retries so it will not easily
> stop the transmission.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> configs/ae350
On Thu, Jan 19, 2023 at 03:05:43PM +0800, Yu Chien Peter Lin wrote:
> Display information about CPU and board during start up.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> configs/ae350_rv32_defconfig | 2 ++
> configs/ae350_rv32_spl_defconfig | 2 ++
> configs/ae350_rv32_spl_xip_de
On Thu, Jan 19, 2023 at 03:05:44PM +0800, Yu Chien Peter Lin wrote:
> This patch fixes following warning for riscv32 compilation.
>
> drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of
> different size [-Wint-to-pointer-cast]
> 122 | regs = (struct l2cache *)dev
On Tue, Jan 03, 2023 at 04:17:13PM +0800, Rick Chen wrote:
> CCTL operations are available to Supervisor/User-mode
> software under the control of the mcache_ctl.CCTL_SUEN
> control bit. Enable it to support Supervisor(and User)
> CCTL operations.
>
> Signed-off-by: Rick Chen
> ---
>
> Changes i
On Wed, Jan 04, 2023 at 09:55:43AM +0800, Rick Chen wrote:
> When fit image boots from ram, the payload will
> be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> In spl fit generic flow, it will malloc another
> memory address and copy whole fit image to this
> malloc address. But it is un-nece
On Wed, Jan 04, 2023 at 09:56:28AM +0800, Rick Chen wrote:
> Add src and dst address checking, if they
> are the same address, just return and don't
> copy data anymore.
>
> Signed-off-by: Rick Chen
> ---
> Changes in v3
> - new patch: separate from [1/2]
> ---
> arch/riscv/lib/memcpy.S | 2 ++
>
Hi Tom,
The following changes since commit ea67f467a43e4c8852bd1ce1bb75f5dc6c3788d1:
Merge branch '2021-10-06-assorted-improvements' (2021-10-06 13:46:31 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to
On Mon, Oct 11, 2021 at 11:14:21AM +0800, Bin Meng wrote:
> On Wed, Sep 15, 2021 at 11:40 AM Leo Liang wrote:
> >
> > On Sun, Sep 12, 2021 at 11:15:08AM +0800, Bin Meng wrote:
> > > The following warning is seen in cache-sifive-ccache.c in a 32-bit build:
> > >
Hi Ilias,
On Tue, Oct 12, 2021 at 12:00:13AM +0300, Ilias Apalodimas wrote:
> At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got
> introduced, in order to support a DTB handed over by an earlier stage boo
typo: boot loader
> loader. However we have another option in the K
On Mon, Oct 18, 2021 at 11:50:05AM +0800, Nick Hu wrote:
> io read/write may cause wrong result because they may read/write data
> from/to register instead of memory. Add 'volatile' to avoid it.
>
> Signed-off-by: Nick Hu
> ---
> arch/riscv/include/asm/io.h | 18 +-
> 1 file chan
Hi Tom,
The following changes since commit fb1018106a7bbb1a0d723029f6760b1b1b4d306d:
Merge branch '2021-10-19-assorted-changes' (2021-10-19 20:45:12 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to ddf
On Mon, Oct 25, 2021 at 03:09:34PM +0200, Heinrich Schuchardt wrote:
> Provide function sbi_get_impl_version() to retrieve the SBI implementation
> version.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/include/asm/sbi.h | 1 +
> arch/riscv/lib/sbi.c | 19 +++
On Mon, Oct 25, 2021 at 03:09:35PM +0200, Heinrich Schuchardt wrote:
> Let the sbi command show the SBI implementation version
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/sbi.c | 26 ++
> 1 file changed, 18 insertions(+), 8 deletions(-)
Reviewed-by: Leo Yu-C
Hi Bin,
On Mon, Nov 01, 2021 at 02:04:48PM +0800, Bin Meng wrote:
> Hi Leo,
>
> On Wed, Oct 27, 2021 at 4:59 PM Leo Yu-Chi Liang
> wrote:
> >
> > According to ./include/linux/kconfig.h,
> > CONFIG_IS_ENABLED(OF_BOARD) expands to 0
> > when CONFIG_SPL_BUILD is defined because
> > there is no CONF
On Fri, Oct 22, 2021 at 02:26:47PM +0530, Padmarao Begari wrote:
> Update compatible as per Microchip PolarFire SoC ethernet
> device node.
>
> Signed-off-by: Padmarao Begari
> ---
> drivers/net/macb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang
On Fri, Oct 22, 2021 at 02:26:48PM +0530, Padmarao Begari wrote:
> UART1 uses for U-BOOT and Linux console instead of UART0 and
> UART0 is reserved for Hart Software Services(HSS).
>
> Signed-off-by: Padmarao Begari
> ---
> doc/board/microchip/mpfs_icicle.rst | 11 +++
> 1 file changed,
On Fri, Oct 22, 2021 at 02:26:44PM +0530, Padmarao Begari wrote:
> The device tree split into .dtsi and .dts files, common
> device node for eMMC/SD, enable I2C1, UART1 for console
> instead of UART0, enable the DDR 2GB memory and in
> that 288MB memory is reserved for fabric buffer.
>
> Signed-of
Hi Padmarao,
On Fri, Oct 22, 2021 at 02:26:45PM +0530, Padmarao Begari wrote:
> This patch updates Microchip MPFS Icicle Kit support. For now,
> add Microchip I2C driver, set environment variables for
> mac addesses and default build for SBI_V02.
typo: addresses
Otherwise,
Review
On Fri, Oct 22, 2021 at 02:26:46PM +0530, Padmarao Begari wrote:
> Add I2C driver code for the Microchip PolarFire SoC.
> This driver supports I2C data transfer and probe for I2C
> slave addresses.
>
> Signed-off-by: Padmarao Begari
> ---
> drivers/i2c/Kconfig | 6 +
> drivers/i2c/Make
On Mon, Nov 01, 2021 at 04:37:32PM +0800, Bin Meng wrote:
> Hi Leo,
>
> On Mon, Nov 1, 2021 at 3:49 PM Leo Liang wrote:
> >
> > Hi Bin,
> > On Mon, Nov 01, 2021 at 02:04:48PM +0800, Bin Meng wrote:
> > > Hi Leo,
> > >
> > > On Wed,
On Mon, Sep 27, 2021 at 12:59:37PM -0700, Thomas Skibo wrote:
> Configure SPI flash devices into SPL. Add SPI boot option to spl.c.
> Document how to format flash for booting.
>
> Signed-off-by: Thomas Skibo
> ---
> .../dts/hifive-unmatched-a00-u-boot.dtsi | 11 +++
> board/sifive/unma
On Mon, Sep 27, 2021 at 12:59:38PM -0700, Thomas Skibo wrote:
> Enable saving environment to SPI flash memory on SiFive
> Unmatched.
>
> Signed-off-by: Thomas Skibo
> ---
> arch/riscv/cpu/fu740/Kconfig | 13 +
> board/sifive/unmatched/Kconfig | 1 +
> 2 files changed, 14 insertion
Hi Tom,
The following changes since commit 52207514ba419a69a8105d16997b025f966c8879:
Merge branch '2021-11-05-Kconfig-syncs' (2021-11-05 15:38:46 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 990e1e4
Hi Xiang,
On Wed, Dec 22, 2021 at 07:32:53AM +0800, Xiang W wrote:
> Various specifications of riscv allow the number of hart to be
> greater than 32. The limit of 32 is determined by
> gd->arch.available_harts. We can eliminate this limitation through
> bitmaps. Currently, the number of hart is li
On Thu, Dec 30, 2021 at 01:55:15AM +0800, Xiang W wrote:
> 在 2021-12-29星期三的 17:23 +0800，Leo Liang写道：
> > Hi Xiang,
> > On Wed, Dec 22, 2021 at 07:32:53AM +0800, Xiang W wrote:
> > > Various specifications of riscv allow the number of hart to be
> > > greater than
On Sun, Jan 09, 2022 at 06:38:55PM +0100, Heinrich Schuchardt wrote:
> EDK II refuses to load the EFI binaries created by U-Boot.
> The reason is an incorrect PE-COFF header. The number of
> data directories does not match NumberOfRvaAndSizes.
> This leads to a failed consistency check in
> PeCoffL
On Sun, Jan 09, 2022 at 09:39:03PM +, Andre Przywara wrote:
> On Sun, 9 Jan 2022 17:30:07 +
> Andre Przywara wrote:
>
> Hi Rick, Leo:
>
> > asm/io.h is the header file containing the central MMIO accessor macros.
> > Judging by the header and the comments, it was apparently once copied
Hi Atish and Heinrich,
On Tue, Oct 13, 2020 at 12:23:31PM -0700, Atish Patra wrote:
> RV32 should use PE32 format instead of PE32+ as the efi header format.
> This requires following changes
> 1. A different header magic value
> 2. An additional parameter known as BaseOfData. Currently, it is set
On Wed, Nov 11, 2020 at 04:25:53PM +0800, Leo Liang wrote:
> Hi Atish and Heinrich,
>
> On Tue, Oct 13, 2020 at 12:23:31PM -0700, Atish Patra wrote:
> > RV32 should use PE32 format instead of PE32+ as the efi header format.
> > This requires following changes
> > 1. A d
Date: Thu, 12 Nov 2020 10:09:52 +0800
From: Leo Yu-Chi Liang
Subject: [PATCH 1/1] riscv: Fix efi header size for RV32
This patch depends on Atish's patch.
(https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.pa...@wdc.com/)
Modify the size of the Optional Header "Wind
On Thu, Nov 12, 2020 at 03:05:23PM +0100, Heinrich Schuchardt wrote:
> On 12.11.20 14:43, Leo Liang wrote:
> > Date: Thu, 12 Nov 2020 10:09:52 +0800
> > From: Leo Yu-Chi Liang
> > Subject: [PATCH 1/1] riscv: Fix efi header size for RV32
> >
> > This patch dep
Date: Tue, 17 Nov 2020 15:36:27 +0800
From: Leo Yu-Chi Liang
Subject: [PATCH 0/3] Complete Optional Header fields in EFI header
These three patches complete the optional header fields in efi header.
Atish's patch was drawn in because CI test would fail at "86. test/py
qemu-riscv32 --> test_efi_s
Date: Tue, 13 Oct 2020 12:23:31 -0700
From: Atish Patra
Subject: [PATCH 1/3] riscv: Fix efi header for RV32
RV32 should use PE32 format instead of PE32+ as the efi header format.
This requires following changes
1. A different header magic value
2. An additional parameter known as BaseOfData. Curr
Date: Thu, 12 Nov 2020 10:09:52 +0800
From: Leo Yu-Chi Liang
Subject: [PATCH 2/3] riscv: Fix efi header size for RV32
This patch depends on Atish's patch.
(https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.pa...@wdc.com/)
Modify the size of the Optional Header "Wind
Date: Mon, 16 Nov 2020 17:07:41 +0800
From: Leo Yu-Chi Liang
Subject: [PATCH 3/3] riscv: Complete efi header for RV32/64
This patch depends on Atish's patch.
(https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.pa...@wdc.com/)
Add fields to complete Optional Header "D
Hi Tom,
The following changes since commit 531c00894577a0a852431adf61ade76925f8b162:
Merge branch '2022-02-08-TI-platform-updates' (2022-02-08 12:28:04 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 7c
Hi Alexandre,
On Fri, Jan 28, 2022 at 02:47:13PM +0100, Alexandre Ghiti wrote:
> The following description is copied from the equivalent patch for the
> Linux Kernel proposed by Aurelien Jarno:
>
> From version 2.38, binutils default to ISA spec version 20191213. This
> means that the csr read/wri
Hi Khem,
On Sun, Feb 13, 2022 at 09:28:45PM -0800, Khem Raj wrote:
> From version 2.38, binutils default to ISA spec version 20191213. This
> means that the csr read/write (csrr*/csrw*) instructions and fence.i
> instruction has separated from the `I` extension, become two standalone
> extensions:
Hi Alex,
On Thu, Feb 17, 2022 at 11:28:46AM +0100, Alexandre Ghiti wrote:
> Hi Leo,
>
> On Thu, Feb 17, 2022 at 10:25 AM Leo Liang wrote:
> >
> > Hi Alexandre,
> > On Fri, Jan 28, 2022 at 02:47:13PM +0100, Alexandre Ghiti wrote:
> > > The following description
Hi Tom,
The following changes since commit ad320c237bea7ece659efaf6c1d43475e0e5db6a:
Merge tag 'u-boot-stm32-20210906' of
https://source.denx.de/u-boot/custodians/u-boot-stm (2021-09-06 10:31:56 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-
On Sat, Sep 11, 2021 at 10:31:23PM +0800, Bin Meng wrote:
> Commit 47d73ba4f4a4 ("board: sifive: overwrite board_fdt_blob_setup in u-boot
> proper")
> added a board-specific implementation of board_fdt_blob_setup() which
> takes a pointer as the return value, but it does not return anything
> if C
On Sun, Sep 12, 2021 at 11:26:45AM -0500, Samuel Holland wrote:
> bootm_low is used as a base address is used to allocate space for the
> FDT blob, initrd, cmdline, etc. when booting Linux. Set the default
> value for RISC-V to the start of the first DRAM bank, so platforms can
> get their DRAM lay
On Sat, Sep 11, 2021 at 01:20:00PM -0400, Sean Anderson wrote:
> The PLL functions take ulong arguments for rate, but still check if that
> rate is negative (which is never true). The correct way to handle this is
> to use IS_ERR_VALUE (like is already done in k210_clk_set_rate). While
> we're at i
On Sat, Sep 11, 2021 at 01:20:01PM -0400, Sean Anderson wrote:
> Everything here sits in a while (true) loop. However, this introduces a
> couple of layers of indentation. We can simplify the code by introducing a
> single goto instead of using continue/break. This will also make adding
> loops in
On Sat, Sep 11, 2021 at 01:20:02PM -0400, Sean Anderson wrote:
> Having to copy-paste the same 3 lines makes adding new test cases
> error-prone. Use a macro.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Simon Glass
> ---
>
> (no changes since v1)
>
> test/dm/k210_pll.c | 30 -
On Sun, Sep 12, 2021 at 09:11:47PM +0200, Heinrich Schuchardt wrote:
> There should be a platform compiled with the new driver.
>
> Enable CONFIG_SYSRESET_SBI for all QEMU boards using SBI.
>
> If you want to test the SBI sysreset driver, disable
> CONFIG_SYSRESET_SYSCON.
>
> Signed-off-by: Heinric
On Sun, Sep 12, 2021 at 11:15:08AM +0800, Bin Meng wrote:
> The following warning is seen in cache-sifive-ccache.c in a 32-bit build:
>
> warning: cast to pointer from integer of different size
> [-Wint-to-pointer-cast]
>
> Fix by casting it with uintptr_t.
>
> Signed-off-by: Bin Meng
> ---
>
>
On Sun, Sep 12, 2021 at 11:15:09AM +0800, Bin Meng wrote:
> dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit
> address and pd->va is a pointer. In a 32-bit build, this causes the
> following warning seen when building sifive-prci.c:
>
> warning: cast to pointer from integer o
On Sun, Sep 12, 2021 at 11:15:10AM +0800, Bin Meng wrote:
> dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit
> address and plat->base is a pointer. In a 32-bit build, this causes the
> following warning seen when building sifive-gpio.c:
>
> warning: cast to pointer from integ
On Sun, Sep 12, 2021 at 11:15:11AM +0800, Bin Meng wrote:
> The following warning is seen in ocores_i2c.c in a 32-bit build:
>
> warning: cast to pointer from integer of different size
> [-Wint-to-pointer-cast]
>
> Change to use dev_read_addr_ptr().
>
> Signed-off-by: Bin Meng
> ---
>
> dr
On Sun, Sep 12, 2021 at 11:15:12AM +0800, Bin Meng wrote:
> At present there is only devfdt_get_addr_ptr() which only returns
> the first pair in the 'reg' property. Add a new API
> devfdt_get_addr_index_ptr() to return the indexed pointer.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/core/fd
On Sun, Sep 12, 2021 at 11:15:13AM +0800, Bin Meng wrote:
> Like dev_read_addr_ptr(), provide a wrapper for the indexed version.
>
> Signed-off-by: Bin Meng
> ---
>
> include/dm/read.h | 18 ++
> 1 file changed, 18 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
On Sun, Sep 12, 2021 at 11:15:15AM +0800, Bin Meng wrote:
> The following warning is seen in sifive_ddr.c in a 32-bit build:
>
> warning: cast to pointer from integer of different size
> [-Wint-to-pointer-cast]
>
> Change to use dev_read_addr_index_ptr().
>
> Signed-off-by: Bin Meng
> ---
>
On Sun, Sep 12, 2021 at 11:15:16AM +0800, Bin Meng wrote:
> The following warning is seen in unleashed.c in a 32-bit build:
>
> warning: cast to pointer from integer of different size
> [-Wint-to-pointer-cast]
>
> Cast with uintptr_t.
>
> Signed-off-by: Bin Meng
> ---
>
> board/sifive/unle
Hi Thomas,
This patch does not apply.
Could you rebase this patchset onto master and then send it again?
Thanks!
Best regards,
Leo
On Mon, Sep 27, 2021 at 12:59:37PM -0700, Thomas Skibo wrote:
> Configure SPI flash devices into SPL. Add SPI boot option to spl.c.
> Document how to format flash f
On Wed, Nov 17, 2021 at 06:21:15PM +0530, Padmarao Begari wrote:
> Remove the microchip compatible string and default compatible "cdns,macb"
> support both 32-bit and 64-bit DMA access.
>
> Signed-off-by: Padmarao Begari
> ---
> drivers/net/macb.c | 18 +++---
> 1 file changed, 7 ins
On Wed, Nov 24, 2021 at 02:32:09PM -0800, Thomas Skibo wrote:
> Configure SPI flash devices into SPL. Add SPI boot option to spl.c.
> Document how to format flash for booting.
>
> Signed-off-by: Thomas Skibo
> ---
> .../dts/hifive-unmatched-a00-u-boot.dtsi | 11 +++
> board/sifive/unma
On Wed, Nov 24, 2021 at 02:32:10PM -0800, Thomas Skibo wrote:
> Enable saving environment to SPI flash memory on SiFive
> Unmatched.
>
> Signed-off-by: Thomas Skibo
> ---
> arch/riscv/cpu/fu740/Kconfig | 13 +
> board/sifive/unmatched/Kconfig | 1 +
> 2 files changed, 14 insertion
Hi Tom,
The following changes since commit 4a14bfffd42f968ed9d72a780a8d44a9053c5b95:
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-11-30
08:59:22 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetc
Hi Alex,
On Mon, Feb 21, 2022 at 05:42:41PM +0100, Alexandre Ghiti wrote:
> On Sat, Feb 19, 2022 at 9:52 AM Leo Liang wrote:
> >
> > Hi Alex,
> > On Thu, Feb 17, 2022 at 11:28:46AM +0100, Alexandre Ghiti wrote:
> > > Hi Leo,
> > >
> > > O
Hi Alex,
On Tue, Mar 01, 2022 at 03:21:56AM +, Leo Liang wrote:
> Hi Alex,
> On Mon, Feb 21, 2022 at 05:42:41PM +0100, Alexandre Ghiti wrote:
> > On Sat, Feb 19, 2022 at 9:52 AM Leo Liang wrote:
> > >
> > > Hi Alex,
> > > On Thu, Feb 17, 2022 at
Hi Alex,
On Thu, Mar 03, 2022 at 11:06:18AM +, Leo Liang wrote:
> Hi Alex,
> On Tue, Mar 01, 2022 at 03:21:56AM +0000, Leo Liang wrote:
> > Hi Alex,
> > On Mon, Feb 21, 2022 at 05:42:41PM +0100, Alexandre Ghiti wrote:
> > > On Sat, Feb 19, 2022 at 9:52 AM Leo Liang
On Tue, Mar 01, 2022 at 10:35:39AM +, Niklas Cassel wrote:
> From: Damien Le Moal
>
> "kendryte" is the marketing name for the K210 RISC-V SoC produced by
> Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210"
> vendor,SoC compatibility string format in the device tree files a
On Tue, Mar 01, 2022 at 10:35:42AM +, Niklas Cassel wrote:
> From: Niklas Cassel
>
> The Linux PLIC interrupt-controller driver actually initializes the hart
> context registers in the PLIC driver exactly in the same order as
> specified in the interrupts-extended device tree property. See th
Hi Tom,
The following changes since commit c149bf41404e34014e37de32fac332892b11bd4a:
Prepare v2022.04-rc4 (2022-03-14 16:39:08 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to aa34e13346cf727197981c599f
On Fri, May 05, 2023 at 09:02:05AM +0100, Ben Dooks wrote:
> Add a link from to the generic one to allow
> things like ubifs to be built. This can be extended with
> riscv AMO ops at a later date.
>
> Signed-off-by: Ben Dooks
> ---
> arch/riscv/include/asm/atomic.h | 14 ++
> 1 file
Hi Ben,
On Fri, May 05, 2023 at 09:02:06AM +0100, Ben Dooks wrote:
> Add implementations of the local_irq_{save,restore} macros so that
> can be used with riscv.
>
> Signed-off-by: Ben Dooks
> ---
> arch/riscv/include/asm/system.h | 15 +++
> 1 file changed, 11 insertions(+), 4 del
On Fri, May 05, 2023 at 09:02:07AM +0100, Ben Dooks wrote:
> These seem to be missing, and trying to build ubifs without them
> is causing errors due to these being missing.
>
> Signed-off-by: Ben Dooks
> ---
> arch/riscv/include/asm/bitops.h | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-
Hi Minda,
On Thu, Jun 01, 2023 at 09:07:14AM +0800, Minda Chen wrote:
>
> Hi Rick and Leo
> Could you review these series patches? Thanks.
> Since patch 1 was acked by Pali， Does it mean patch 1 is accepted？
I think acked-by means that the patch is considered good enough to be merged.
Aside fr
On Tue, May 09, 2023 at 02:50:05PM +0100, Ben Dooks wrote:
> If we're building non FU540/FU740 SoC drivers, then the sifive-prci.o
> is not needed. Only build this when CONFIG_CLK_SIFIVE_PRCI is selected.
>
> Signed-off-by: Ben Dooks
> ---
> drivers/clk/sifive/Makefile | 4 +---
> 1 file changed
Hi Tom,
The following changes since commit 4f1077bc35f683985ff77e442ada7e8a8a52e3b7:
Prepare v2023.07-rc5 (2023-06-26 11:44:06 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git riscv-fixes
for you to fetch changes up to 4a3efd71cd858b8
Hi Rick, Bin,
On Tue, Jun 27, 2023 at 09:12:35AM +0800, Bin Meng wrote:
> On Tue, Jun 27, 2023 at 8:50 AM Rick Chen wrote:
> >
> > > From: Bin Meng
> > > Sent: Wednesday, June 21, 2023 11:07 PM
> > > To: u-boot@lists.denx.de
> > > Cc: Andrew Scull ; Leo Yu-Chi Liang(梁育齊)
> > > ; Rick Jian-Zhi Ch
Hi YiXun,
On Fri, May 26, 2023 at 08:41:04PM +0800, Yixun Lan wrote:
> Add support for Sipeed's Lichee Pi 4A board which based on
> T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled,
> so it's capable of chain booting from T-HEAD's vendor u-boot.
>
> Reviewed-by: Wei Fu
Hi YiXun,
On Fri, May 26, 2023 at 08:41:07PM +0800, Yixun Lan wrote:
> Reviewed-by: Wei Fu
> Signed-off-by: Yixun Lan
> ---
> doc/board/index.rst | 1 +
> doc/board/thead/index.rst | 9 +++
> doc/board/thead/lpi4a.rst | 112 ++
> 3 files changed, 12
On Sun, Aug 11, 2024 at 11:51:09AM +0200, Heinrich Schuchardt wrote:
> [EXTERNAL MAIL]
>
> The CONFIG_SPL_FRAMEPOINTER symbol is only relevant in SPL.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang
On Sun, Aug 11, 2024 at 01:01:03PM +0200, Heinrich Schuchardt wrote:
> [EXTERNAL MAIL]
>
> To minimize SPL size it is reasonable to disable SHOW_REGS. For main U-Boot
> the size restrictions are much more relaxed.
>
> * Provide separate Kconfig symbols for SPL and main U-Boot.
> * Add a help text
On Sun, Aug 11, 2024 at 01:01:04PM +0200, Heinrich Schuchardt wrote:
> [EXTERNAL MAIL]
>
> If an exception occurs in main U-Boot, show the registers. This makes
> analyzing crashes especially in external applications easier.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/Kconfig | 1
On Sun, Aug 11, 2024 at 04:41:23PM +0200, Heinrich Schuchardt wrote:
> [EXTERNAL MAIL]
>
> Some versions of KVM don't allow access to the cycle CSR.
>
> Provide a command 'exception rdcycle' for testing.
>
> If the cycle CSR is accessible, we get an output like:
>
> => exception rdcycle
>
On Sat, Feb 17, 2024 at 12:18:04AM +0100, Heinrich Schuchardt wrote:
> The existing code is unnecessarily convoluted:
>
> Arrays __prci_init_clocks_fu[5|7]40 are initialized with data.
> In separate includes fu[5|7]40-prci.h the size of the arrays is provided as
> constants.
>
> By moving the st
On Tue, Jun 11, 2024 at 05:41:13PM +0800, Kongyang Liu wrote:
> Import header file of sophgo cv1800b clock controller from kernel
>
> Signed-off-by: Kongyang Liu
> Link:
> https://lore.kernel.org/all/ia1pr20mb4953637e7a6c121d7a700f1cbb...@ia1pr20mb4953.namprd20.prod.outlook.com/
> ---
>
> (no c
On Tue, Jun 11, 2024 at 05:41:14PM +0800, Kongyang Liu wrote:
> Add clock controller driver for sophgo cv1800b SoC
>
> Signed-off-by: Kongyang Liu
> ---
>
> Changes in v2:
> - Fix compilation error
> - Remove unused code
>
> drivers/clk/Kconfig | 1 +
> drivers/clk/Makefile
On Tue, Jun 11, 2024 at 05:41:15PM +0800, Kongyang Liu wrote:
> Add configs to enable clock controller for Sophgo Milk-V Duo board
>
> Signed-off-by: Kongyang Liu
> ---
>
> (no changes since v1)
>
> configs/milkv_duo_defconfig | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
R
On Tue, Jun 11, 2024 at 05:41:16PM +0800, Kongyang Liu wrote:
> Replace device clocks with real clocks from the clock controller, and
> remove dummy clocks.
>
> Signed-off-by: Kongyang Liu
> ---
>
> (no changes since v1)
>
> arch/riscv/dts/cv18xx.dtsi | 40 +++--
On Thu, Jul 18, 2024 at 12:33:22PM +0800, Kongyang Liu wrote:
> Add basic support for SpacemiT's Banana Pi F3 board
>
> Signed-off-by: Kongyang Liu
> ---
>
> Changes in v2:
> - Change license to GPL-2.0-or-later
> - Add memory node for dts
> - Add ft_board_setup function for kernel memory init
>
On Thu, Jul 18, 2024 at 12:33:23PM +0800, Kongyang Liu wrote:
> Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC.
>
> Signed-off-by: Kongyang Liu
> ---
>
> (no changes since v1)
>
> doc/board/index.rst| 1 +
> doc/board/spacemit/bananapi_f3.rst | 78 +++
On Sat, Jul 20, 2024 at 01:11:58AM +0200, Heinrich Schuchardt wrote:
> For the Milk-V Mars CM (lite) we have only been copying sizeof(void *)
> bytes to the compatible property instead of the whole string list.
>
> Fixes: de3229599d4f ("board: add support for Milk-V Mars CM")
> Reported-by: E Shat
On Fri, Jul 26, 2024 at 03:07:21PM +0300, Maxim Kochetkov wrote:
> These seem to be missing, and trying to build fastboot cmd without
> them is causing errors due to these being missing.
>
> Signed-off-by: Maxim Kochetkov
> Tested-by: E Shattow ---
> arch/riscv/include/asm/bitops.h | 40 +++
Hi Eva,
The other two patches of this patch series are accidently sent via "Reply".
Could you please re-send this series of patches to mailing list?
Other than that, LGTM.
Reviewed-by: Leo Yu-Chi Liang
On Wed, Jul 17, 2024 at 09:22:26PM +0300, Eva Kurchatova wrote:
> [EXTERNAL MAIL]
>
> From
On Thu, Jun 27, 2024 at 02:26:00PM +0800, Jacky Chou wrote:
> When executing TFTP, the ARP will be replied to after receiving
> the ARP. U-boot's ARP routine modifies the data in the receive
> packet in response to the ARP packet and then copies it
> into the transmit packet.
> At this point, the r
On Fri, Jun 28, 2024 at 03:14:45PM +0800, Jacky Chou wrote:
> The NC-SI interface does not need the MDIO bus and the
> NC-SI PHY device cannot get from dm_eth_phy_connect.
> Therefore, use phy_connect directly here.
>
> Signed-off-by: Jacky Chou
> ---
> drivers/net/ftgmac100.c | 2 +-
> 1 file c
On Fri, Jun 28, 2024 at 05:38:50PM +0800, Jacky Chou wrote:
> The TX/RX descriptor size is 16 byte.
> When the cache line size is larger than 16 bytes, descriptors
> flushed to RAM will flush more than one descriptor.
> It is possible that it may mistakenly flush to other descriptor
> that has been
On Mon, Jul 08, 2024 at 02:07:18PM +0800, Jacky Chou wrote:
> Add support of Aspeed AST2700 SoC. AST2700 is based on ARM64 so modify
> the DMA address related code to fit both ARM and ARM64. Besides, the
> RMII/RGMII mode control register is moved from SCU500 to MAC50 so
> initialize the register
On Mon, Aug 19, 2024 at 06:16:57PM +0800, Chia-Wei Wang wrote:
> Make the Atomic (A) ISA extension selectable. Thus CPUs such as
> Ibex without the A extension can be supported.
>
> Signed-off-by: Chia-Wei Wang
> ---
> arch/riscv/Kconfig | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-
On Mon, Aug 19, 2024 at 06:16:58PM +0800, Chia-Wei Wang wrote:
> Add prompt for STACK_SIZE_SHIFT to make it configurable.
> The default value remains 14 as usual.
>
> Signed-off-by: Chia-Wei Wang
> ---
> arch/riscv/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo
On Mon, Aug 19, 2024 at 06:17:00PM +0800, Chia-Wei Wang wrote:
> AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
> for the first stage bootloader execution, namely SPL.
>
> This patch implements the preliminary base to successfully run SPL
> on this RV32-based MCU to the console
On Mon, Aug 19, 2024 at 06:16:59PM +0800, Chia-Wei Wang wrote:
> The _image_binary_end symbol was aligned to the 8-bytes boundary.
> However, the SPL device tree (u-boot-spl.dtb) is concatenated right
> after the binary (u-boot-spl-nodtb.bin) wihtout the consideration of
> the 8-bytes alignment res
On Mon, Aug 19, 2024 at 06:17:01PM +0800, Chia-Wei Wang wrote:
> Add the driver for the AST2700 Ibex timer, which uses CPU
> cycles as the timer count running at 200MHz.
>
> Signed-off-by: Chia-Wei Wang
> ---
> drivers/timer/Kconfig | 6 +
> drivers/timer/Makefile | 1 +
>
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