On Mon, Sep 05, 2011 at 02:37:29PM +0200, Wolfgang Denk wrote:
> Signed-off-by: Wolfgang Denk
> Cc: Albert ARIBAUD
> Cc: George G. Davis
Ack, Thanks!
--
Regards,
George
> ---
> MAINTAINERS |4 -
> board/gcplus/Makefile| 53 -
> b
rn, c7, c7, 0 @ Clean &
invalidate D-Cache" instruction to insure that memory is consistent
with any dirty cache lines.
Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
used.
Signed-of
rn, c7, c7, 0 @ Clean &
invalidate D-Cache" instruction to insure that memory is consistent
with any dirty cache lines.
Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
used.
Signed-of
Hello Dirk,
On Mon, May 10, 2010 at 10:02 AM, Dirk Behme wrote:
>
> Hi George,
>
> On 05.05.2010 23:09, George G. Davis wrote:
>>
>> The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
>> instruction which means "Invalidate Both
Hello Wolfgang,
On Tue, May 11, 2010 at 4:56 AM, Wolfgang Denk wrote:
> Dear "George G. Davis",
>
> In message
> you wrote:
> >
> > > Why don't we have to invalidate/flush the I- and BT-Cache here? I.e.
> why
> > is it sufficient to clean &
Ping,
On Thu, May 13, 2010 at 11:41:13AM +0200, Dirk Behme wrote:
> On 11.05.2010 16:15, gda...@mvista.com wrote:
> >From: George G. Davis
> >
> >The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
> >instruction which means "Inval
Hi Tom,
On Tue, Jun 01, 2010 at 09:38:56AM -0500, Tom Rix wrote:
> gda...@mvista.com wrote:
> >From: George G. Davis
> >
> >The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
> >instruction which means "Invalidate Both Caches&q
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