T4/B4 SoC's have a different version of ISBC. The secure boot
functionality is different with the new version of ISBC
compared to the earlier SoC's. So the version information is added
in file config_mpc85xx.h
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
-
-off-by: Aneesh Bansal
---
arch/powerpc/cpu/mpc85xx/cpu_init.c| 28 +++-
arch/powerpc/cpu/mpc85xx/start.S | 3 ++-
arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++
boards.cfg | 1 +
4 files changed, 32 insertions
T4/B4 SoC's have a different version of ISBC. The secure boot
functionality is different with the new version of ISBC
compared to the earlier SoC's. So the version information is added
in file config_mpc85xx.h
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
-
-off-by: Aneesh Bansal
---
arch/powerpc/cpu/mpc85xx/cpu_init.c| 28 +++-
arch/powerpc/cpu/mpc85xx/start.S | 3 ++-
arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++
boards.cfg | 1 +
4 files changed, 32 insertions
In case of secure boot, boot from NAND is ramboot.
It was removed by some other commit. So defining it again.
Signed-off-by: Aneesh Bansal
---
include/configs/P1010RDB.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
The workaround for IFC errata A003399 was not enabled
in case of secure boot. So, secure boot from NOR was not
working.
Signed-off-by: Aneesh Bansal
---
include/configs/P1010RDB.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/configs/P1010RDB.h b/include/configs
ISBC creates a LAW 0 entry for non PBL platforms, which is not
disabled before transferring the control to uboot.
The LAW 0 entry has to be disabled.
Signed-off-by: Aneesh Bansal
---
arch/powerpc/cpu/mpc85xx/start.S | 58
1 file changed, 58 insertions
-off-by: Aneesh Bansal
---
README | 4
arch/powerpc/cpu/mpc85xx/cpu_init.c| 27 ++-
arch/powerpc/cpu/mpc85xx/start.S | 3 ++-
arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++
boards.cfg
-off-by: Aneesh Bansal
---
README | 4
arch/powerpc/cpu/mpc85xx/cpu_init.c| 27 ++-
arch/powerpc/cpu/mpc85xx/start.S | 3 ++-
arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++
boards.cfg
.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
Changes in v3:
- Updated MAINTAINERS file
- In
area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.
Signed-off-by: Aneesh Bansal
In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND.
Signed-off-by: Aneesh Bansal
---
include
area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.
Signed-off-by: Aneesh Bansal
Signed
area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.
Signed-off-by: Aneesh Bansal
Signed
ISBC creates a LAW 0 entry for non PBL platforms, which is not
disabled before transferring the control to uboot.
The LAW 0 entry has to be disabled.
Signed-off-by: Aneesh Bansal
---
arch/powerpc/cpu/mpc8xxx/law.c | 10 ++
1 file changed, 10 insertions(+)
Changes from v1:
The LAW was
Add NOR, SPI and SD secure boot targets for BSC9132QDS.
Changes:
- Debug TLB entry is not required for Secure Boot Target.
Signed-off-by: Aneesh Bansal
---
arch/powerpc/cpu/mpc85xx/start.S | 9 ++---
arch/powerpc/include/asm/fsl_secure_boot.h | 2 ++
boards.cfg
In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND
Signed-off-by: Aneesh Bansal
---
boards.cfg
-off-by: Aneesh Bansal
---
README | 4
arch/powerpc/cpu/mpc85xx/cpu_init.c| 27 ++-
arch/powerpc/cpu/mpc85xx/start.S | 3 ++-
arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++
boards.cfg
Secure Boot Target is added for T4240QDS and T4160QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS.
Signed-off-by: Aneesh Bansal
---
arch/powerpc/include/asm
Secure Boot Target is added for T2080QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS.
Signed-off-by: Aneesh Bansal
---
arch/powerpc/include/asm/fsl_secure_boot.h | 4
t1040qds
T1040QDS_SECURE_BOOT T1040QDS:PPC_T1040,SECURE_BOOT
Aneesh Bansal
Active powerpc mpc85xx- freescale t104xrdb
T1040RDB
T1040RDB.h file is removed and a unified file T104xRDB.h is created.
Hence macro CONFIG_T1040 is renamed to CONFIG_T104x.
Signed-off-by: Gaurav Kumar Rana
Signed-off-by: Aneesh Bansal
---
arch/powerpc/include/asm/fsl_secure_boot.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Secure Boot Target is added for T2080RDB
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB.
Signed-off-by: Aneesh Bansal
---
arch/powerpc/include/asm/fsl_secure_boot.h | 1
In case of NAND boot, CSPR0 is configured as NAND and CSPR1
is configured as NOR.
Signed-off-by: Aneesh Bansal
---
include/configs/BSC9132QDS.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index e76a04b..7bb5d33
In case of secure boot from NAND, CSPR and FTIM settings are
same as non-secure NAND boot. CSPR0 is configured as NAND and
CSPR1 is configured as NOR.
Signed-off-by: Aneesh Bansal
---
include/configs/BSC9132QDS.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal
---
Changes in v2:
Compile time warning removed when
to Job Rings are done
using I/O functions defined for SEC which will take care of
the endianness.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal
---
Changes in v2:
sec_out_phys and sec_in_phys has
Data types and I/O functions have been defined for
64 bit physical addresses in arm.
Signed-off-by: Aneesh Bansal
---
Changes in v2:
There is no need for defining 64 bit I/O operations.
If an IP needs to do 64 bit access, it will do it by defining
32 bit addr_hi and addr_lo.
arch/arm/include
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal
---
Changes in v2:
Compile time warning removed when
where endianness of CAAM and core is
different.
Signed-off-by: Aneesh Bansal
CC: Alex Porosanu
---
drivers/crypto/fsl/jr.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index f63eacb..b553e3c 100644
--- a/drivers/crypto
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 16 --
.../include/asm
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal
---
arch/arm/cpu/armv8/generic_timer.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv8/generic_timer.c
b/arch/arm/cpu/armv8/generic_timer.c
index
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch
: Aneesh Bansal
---
arch/arm/include/asm/types.h | 2 ++
arch/powerpc/include/asm/types.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index 388058e..765 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm
where endianness of CAAM and core is
different.
Signed-off-by: Aneesh Bansal
CC: Alex Porosanu
---
Changes in v2:
New Patch Set created with an additional patch.
drivers/crypto/fsl/jr.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal
---
Changes in v2:
New Patch Set created with an additional patch
Commit Subject modified
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +
1 file
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal
---
Changes in v2:
New Patch Set created with an additional patch.
Pointers typecasted
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal
---
Changes in v2:
New Patch Set created with an additional patch.
arch/arm/cpu/armv8/generic_timer.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/cpu
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal
---
Changes in v3:
- Enabled CONFIG_SYS_NS16550=y, CONFIF_DM=y and other options
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal
---
Changes in v4:
- Fixed compilation break for LS1021AQDS
arch/arm/include/asm/arch
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
New Patch set created with an additional patch
Commit Subject
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal
---
Changes in v5:
- Commit Subject modified
- Call to sec_init() placed under
where endianness of CAAM and core is
different.
Signed-off-by: Aneesh Bansal
CC: Alex Porosanu
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None (New Patch set created with an additional patch)
drivers/crypto/fsl/jr.c | 8 ++--
1 file changed, 2 insertions
typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by: Aneesh Bansal
---
Changes in v5:
New patch instead of http://patchwork.ozlabs.org/patch/546319/
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/compiler.h| 3 ---
include/linux/types.h
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal
---
Changes in v5:
- Commit Subject modified
Changes in v4: None
Changes in v3: None
Changes in v2: None (New Patch set created with an additional patch)
arch/arm/cpu/armv8
[PATCH 5/5, v5] drivers/crypto/fsl: fix endianness issue in RNG
http://patchwork.ozlabs.org/patch/553822/
Aneesh Bansal (4):
SECURE BOOT: change prototype of fsl_secboot_validate function
SECURE BOOT: separate functions for reading keys
SECURE BOOT: separate function created for signature
Separate functions are created for reading and checking the
sanity of Public keys:
- read_validate_single_key
- read_validate_ie_tbl
- read_validate_srk_table
Signed-off-by: Saksham Jain
Signed-off-by: Aneesh Bansal
---
board/freescale/common/fsl_validate.c | 169
The prototype and defination of function fsl_secboot_validate
has been changed to support calling this function from another
function within u-boot.
Only two aruments needed:
1) header address - Mandatory
2) SHA256 string - optional
Signed-off-by: Saksham Jain
Signed-off-by: Aneesh Bansal
The code for image hash calculation, hash calculation from
RSA signature and comparison of hashes has been mobed to a
separate function.
Signed-off-by: Saksham Jain
Signed-off-by: Aneesh Bansal
---
board/freescale/common/fsl_validate.c | 98 +++
1 file changed
to the function, the address
field in Header is not read and is treated as a reserved
field.
Signed-off-by: Saksham Jain
Signed-off-by: Aneesh Bansal
---
board/freescale/common/cmd_esbc_validate.c | 10 ++---
board/freescale/common/fsl_validate.c | 33
For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.
Signed-off-by: Aneesh Bansal
---
Changes in v8:
New Patchset Created
arch/powerpc/include/asm
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.
The targets for P5020 and P5040 are added in the same manner.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
.
Signed-off-by: Aneesh Bansal
---
Changes in v8:
New Patchset Created
Makefile | 4
arch/powerpc/cpu/mpc85xx/start.S | 11 +++
arch/powerpc/include/asm/fsl_secure_boot.h | 5 +
board/freescale/common/p_corenet/tlb.c | 15
arch-ls102xa/config.h to
arm/include/asm/fsl_secure_boot.h
Signed-off-by: Aneesh Bansal
---
Changes in v8:
New Patch added in patchset
arch/arm/include/asm/arch-ls102xa/config.h | 14 --
arch/arm/include/asm/fsl_secure_boot.h | 22 ++
arch/powerpc/include/asm
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal
---
board/freescale/common/fsl_validate.c | 18
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal
---
board/freescale/common/fsl_validate.c | 18
Data types and I/O functions have been defined for
64 bit physical addresses in arm and powerpc
Signed-off-by: Aneesh Bansal
---
arch/arm/include/asm/io.h | 4 +++-
arch/arm/include/asm/types.h | 13 -
arch/powerpc/include/asm/io.h | 13 +
3 files changed, 24
using I/O functions
defined for SEC which will take care of the endianness.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal
---
drivers/crypto/fsl/desc_constr.h | 24
drivers
Data types and I/O functions have been defined for
64 bit physical addresses in arm.
Signed-off-by: Aneesh Bansal
---
Changes in v3:
Corrected the definition of virt_to_phys() and definition of phys_addr_t.
arch/arm/include/asm/io.h| 4 ++--
arch/arm/include/asm/types.h | 10 +++---
2
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal
---
Changes in v3:
Patch Rebased and removed compile time
to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal
---
Changes in v3:sec_out_phys and
The compilation of u-boot-dtb.img should be controlled by
CONFIG_OF_CONTROL and not CONFIG_DM.
CONFIG_DM may be defined even without Device Tree requirement.
This was added in commit 947cee1127c5fa97529c8cda4f0b48d141f92560.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
CC: Alison
.
Signed-off-by: Aneesh Bansal
---
include/configs/C29XPCIE.h | 4
include/configs/T102xQDS.h | 12 +++-
include/configs/T102xRDB.h | 12 +++-
include/configs/T1040QDS.h | 3 ++-
include/configs/T104xRDB.h | 3 ++-
include/configs/T208xQDS.h
For ARM based SoC's there is no need to add a separate target/defconfig
for Secure Boot. Boot Mode can be determined at run time to continue
the chain of trust.
The patch set is dependent on following:
http://patchwork.ozlabs.org/patch/560391/
http://patchwork.ozlabs.org/patch/553826/
A
CONFIG_CMD_BLOB must be defined in case of Secure Boot.
It was earlier defined in all config files. The definition
has been moved to a common file which is included by all configs.
Signed-off-by: Aneesh Bansal
---
arch/arm/include/asm/fsl_secure_boot.h | 1 +
arch/powerpc/include/asm
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal
---
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +
arch/powerpc/include/asm/immap_8
variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal
---
arch/powerpc/cpu/mpc85xx/cpu_init.c| 12
arch/powerpc/include/asm/fsl_secure_boot.h | 7 +++
2 files changed, 19
ll be required
for Secure Boot. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be
determine at run time.
Signed-off-by: Aneesh Bansal
---
arch/arm/include/asm/fsl_secure_boot.h | 6 +-
arch/powerpc/include/asm/fsl_secure_boot.h | 35 +
board/freescale/common/Makefi
In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.
Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.
Signed-off-by: Aneesh
environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4
board/freescale/common/Makefile | 1 +
board/freescale
.
Signed-off-by: Saksham Jain
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
Changes in v7:
Created TLB entry to map virtual address 0xFFF0 to physical address
0xBFF0 as per discussion.
Makefile | 4
arch/powerpc/cpu/mpc85xx
Signed-off-by: Aneesh Bansal
---
Changes in v7:
Patchset created.
TEXT BASE is defined as 0xFFF4 as per new design.
board/freescale/corenet_ds/MAINTAINERS | 2 ++
configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4
configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4
3 files changed, 10
For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.
Signed-off-by: Saksham Jain
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
Changes
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.
The targets for P5020 and P5040 are added in the same manner.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
Changes in v4:
- Created a patch set
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.
The targets for P5020 and P5040 are added in the same manner.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
Changes in v5:
Created MACRO's for addres
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.
The targets for P5020 and P5040 are added in the same manner.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
Changes in v6:
Changed the version in Patchset
The ITS bit was being read incorrectly beacause of operator
precedence. The same ahs been corrected.
Signed-off-by: Lawish Deshmukh
Signed-off-by: Aneesh Bansal
---
board/freescale/common/fsl_validate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/common
to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal
---
Changes in v4:
Removed compile
to Job Rings will
be depend on endianness of SEC block as 32 bit low and
high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
descriptor will vary depending on endianness of SEC.
Signed-off-by: Aneesh Bansal
---
Changes in v5:
Removed compile
While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.
Signed-off-by: Aneesh Bansal
---
arch/powerpc/cpu/mpc85xx/start.S | 23 +++
1 file changed
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Tuesday, April 19, 2016 10:03 PM
> To: Aneesh Bansal ; u-boot@lists.denx.de
> Cc: Ruchika Gupta ; Prabhakar Kushwaha
>
> Subject: Re: [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before enabling
> >>> While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
> >>> error checking enable) must not be changed while the L2 cache is enabled.
> >>> So, L2PE must be set before enabling L2 cache.
> >>
> >> Aneesh,
> >>
> >> The original code set L2PE and L2E together. The L2PE bit doesn't ch
> -Original Message-
> From: Saksham Jain [mailto:saksham.j...@nxp.com]
> Sent: Monday, February 01, 2016 5:14 PM
> To: u-boot@lists.denx.de
> Cc: york sun ; Ruchika Gupta ;
> Prabhakar Kushwaha ; Saksham Jain
> ; Aneesh Bansal
> Subject: [PATCH v3 15/15] SEC
> -Original Message-
> From: Huan Wang
> Sent: Tuesday, February 02, 2016 12:31 PM
> To: york sun ; Aneesh Bansal ; u-
> b...@lists.denx.de; Huan Wang-B18965
> Cc: Ruchika Gupta ; Prabhakar Kushwaha
> ; Nitesh Lal
> Subject: RE: [PATCH v3] Enable snooping on tran
chika Gupta
Signed-off-by: Nitesh Narayan Lal
Signed-off-by: Aneesh Bansal
---
Changes in v4:
- Modified the Commit message
- Functionality moved to SoC Specific file
The patch is dependent on
http://patchwork.ozlabs.org/patch/579377/
arch/arm/cpu/armv7/ls102xa/soc.c | 5 +++
> -Original Message-
> From: york sun
> Sent: Wednesday, February 10, 2016 10:51 AM
> To: Scott Wood ; Aneesh Bansal
> Cc: u-boot@lists.denx.de; Ruchika Gupta ;
> Prabhakar
> Kushwaha
> Subject: Re: [PATCH 2/3][v3] Data types defined for 64 bit physical address
When CAAM runs a descriptor and an error occurs, a non-zero
value is set in Output Status Register.
The if condition should check the status for a non-zero value.
Signed-off-by: Aneesh Bansal
---
drivers/crypto/fsl/jr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
Structures have been defined for PDB (Protocol Data Blcks)
for various operations.
These structure will be used to add PDB data while creating
the PDB descriptors.
CC: Ulises Cardenas
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
drivers/crypto/fsl/desc.h | 55
Construct API's have been added to create Protocol Descriptors
for CAAM block.
CC: Ulises Cardenas
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
drivers/crypto/fsl/desc.h| 25 +
drivers/crypto/fsl/desc_constr.h
As part of Secure Boot Chain of trust, PPA image must be validated
before the image is started.
The code for the same has been added.
Signed-off-by: Aneesh Bansal
---
The patchset is dependent on
http://patchwork.ozlabs.org/patch/571339/
arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 22
sec_init() which was earlier called in misc_init_r()
is now done in board_init() before PPA init as SEC
block will be used during PPA image validation.
Signed-off-by: Aneesh Bansal
---
The patchset is dependent on
http://patchwork.ozlabs.org/patch/571339/
board/freescale/ls1043ardb
case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
Makefile | 4
case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on this SRAM at
location 0xBFF4 with entry point as 0xBFFC.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
Changes in v2:
set_tlb call moved inside the if
Define CONFIG_FSL_CAAM for LS2080 which would enable
call to sec_init() during U-Boot.
Signed-off-by: Aneesh Bansal
---
include/configs/ls2080a_common.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 13ce349
Gupta
Signed-off-by: Aneesh Bansal
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 +
arch/powerpc/cpu/mpc8xxx/Makefile | 1 +
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 449 ++
arch/powerpc/cpu/mpc8xxx/pamu_table.c | 57 +
arch/powerpc/include/asm/fsl_pamu.h
This reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
Signed-off-by: Aneesh Bansal
CC: Ruchika Gupta
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 +
arch/powerpc/include/asm/immap_85xx.h | 1 -
2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/powerpc/cpu
This reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
PAMU should not be by-passed in case of Secure Boot.
Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
---
Changes in v2:
Modified the commit message
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 +
arch/powerpc
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