78cab an out of bound access occurs. See
> > below.
> >
> > On 11/4/15 10:48 PM, Andy Fleming wrote:
> > > This board runs a P5020 or P5040 chip, and utilizes
> > > an EEPROM with similar formatting to the Freescale P5020DS.
> > >
> > > Large am
On Fri, Oct 3, 2008 at 10:46 AM, Haiying Wang
<[EMAIL PROTECTED]> wrote:
> MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
> according to the board spec, and adds the 2nd i2c bus offset.
>
> Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
Applied 1-3, and they were pu
On Fri, Oct 3, 2008 at 11:36 AM, Haiying Wang
<[EMAIL PROTECTED]> wrote:
> Fix some bugs:
> 1. Correctly set intlv_ctl in cs_config.
> 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
> 3. Set base_address and total memory for each ddr controller in memory
> control
On Wed, Oct 8, 2008 at 3:36 PM, Kumar Gala <[EMAIL PROTECTED]> wrote:
> Commit 445a7b38308eb05b41de74165b20855db58c7ee5 introduced the following
> compile warnings:
>
> cmd_i2c.c:112: warning: missing braces around initializer
> cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]')
>
On Sat, Sep 27, 2008 at 1:40 AM, Jason Jin <[EMAIL PROTECTED]> wrote:
> On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
> The display is still sync mode DDR freq. This patch try to fix
> this. The display DDR freq is now the actual freq in both
> sync and async mode.
>
> Signe
On Wed, Oct 8, 2008 at 6:41 AM, Rafal Czubak <[EMAIL PROTECTED]> wrote:
> get_cpu_board_revision() returned board revision based on information stored
> in global static struct eeprom. It should instead use one from local struct
> board_eeprom, to which the data is actually read from EEPROM. The bu
On Sun, Oct 12, 2008 at 11:18 PM, Ben Warren <[EMAIL PROTECTED]> wrote:
> Wolfgang Denk wrote:
>> Dear Ben,
>>
>> In message <[EMAIL PROTECTED]> Andre Schwarz wrote:
>>
>>> Currently VSC8601 doesn't link with 10/100M partners if the
>>> EEPROM/Strapping is not set up.
>>> Setting the auto-neg regis
On Tue, Sep 23, 2008 at 5:05 AM, Bartlomiej Sieka <[EMAIL PROTECTED]> wrote:
> Hello,
>
> TOT U-Boot (commit 8fd4166c, compiled with ELDK 4.2) for the MPC8555CDS
> target is broken with the following symptoms:
>
>
> [flash the 8fd4166c image and reset the board]
>
> U-Boot 2008.10-rc2-00018-g8fd416
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout
<[EMAIL PROTECTED]> wrote:
> Signed-off-by: Ed Swarthout <[EMAIL PROTECTED]>
Acked-by: Andy Fleming <[EMAIL PROTECTED]>
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On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout
<[EMAIL PROTECTED]> wrote:
> Signed-off-by: Ed Swarthout <[EMAIL PROTECTED]>
Applied to 85xx-next
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On Wed, Oct 8, 2008 at 11:37 PM, Ed Swarthout
<[EMAIL PROTECTED]> wrote:
> Signed-off-by: Ed Swarthout <[EMAIL PROTECTED]>
Applied to 85xx-next
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On Thu, Oct 9, 2008 at 12:29 AM, Ed Swarthout
<[EMAIL PROTECTED]> wrote:
> mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0.
> Include host_agent == 0 decode for end-point determination.
>
> This is not needed for the ds reference board since pcie3 will be a host
> in order
On Thu, Oct 9, 2008 at 1:25 AM, Ed Swarthout <[EMAIL PROTECTED]> wrote:
> Debug sessions may have left enabled laws.
> Changing lawbar with an unkown enabled tgtid could cause problems.
>
> Signed-off-by: Ed Swarthout <[EMAIL PROTECTED]>
Applied to 85xx-next
___
On Thu, Oct 9, 2008 at 1:26 AM, Ed Swarthout <[EMAIL PROTECTED]> wrote:
> This allows a second core to restart without causing a PIC reset.
>
> Internal interupt changes:
> Enable L2 error interrupt IIVPR0 and give it vector 0x100.
> Use correct interrupt (8) for mpc8572 pcie3.
> Add pcie3 interrup
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout
<[EMAIL PROTECTED]> wrote:
>
> Signed-off-by: Ed Swarthout <[EMAIL PROTECTED]>
Applied to 85xx-next
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On Thu, Oct 9, 2008 at 10:40 PM, Jason Jin <[EMAIL PROTECTED]> wrote:
> From: Liu Yu <[EMAIL PROTECTED]>
>
> The pixis sgmii command depend on the FPGA support on the board, some 85xx
> boards support SGMII riser card but did not support this command, define
> CONFIG_PIXIS_SGMII_CMD for those board
On Thu, Oct 9, 2008 at 10:40 PM, Jason Jin <[EMAIL PROTECTED]> wrote:
> From: Liu Yu <[EMAIL PROTECTED]>
>
> This patch based on Andy's work.
> Including command 'pixis_set_sgmii' support.
>
> Signed-off-by: Liu Yu <[EMAIL PROTECTED]>
Applied to 85xx-next
__
On Thu, Oct 9, 2008 at 10:41 PM, Jason Jin <[EMAIL PROTECTED]> wrote:
> Signed-off-by: Jason Jin <[EMAIL PROTECTED]>
Applied to 85xx-next
Andy
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will hangup.
>> This patch try to fix this by reading the serdes status before the
>> SATA
>> initialize.
>>
>> Signed-off-by: Jason Jin <[EMAIL PROTECTED]>
Acked-by: Andy Fleming <[EMAIL PROTECTED]>
Wolfgang, if you want, I can apply this to my master branch
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git 85xx-next
Andy Fleming (1):
Have u-boot pass stashing parameters into device tree
Ed Swarthout (5):
pixis do not print long help if not configured
85xx if NUM_CPUS>1, print cpu num
. Here is the correct request:
Andy Fleming (1):
Have u-boot pass stashing parameters into device tree
Ed Swarthout (5):
pixis do not print long help if not configured
85xx if NUM_CPUS>1, print cpu number
mpc8572 additional end-point mode
fsl_law clear enable bef
On Tue, Oct 21, 2008 at 9:59 AM, Wolfgang Denk <[EMAIL PROTECTED]> wrote:
> Dear Peter Tyser,
>
>> > Timestamps are not suitable to provide this type of information. If
>> > you care about which code you are running, than make sure to use git.
>>
>> I do, but the minor annoyance of having the ex
On Oct 23, 2008, at 01:47, Kumar Gala wrote:
> Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle
> e500mc's 64-byte cacheline properly when it gets added.
>
> Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
Grabbed this one and the e500mc one, thanks
Andy
_
On Oct 23, 2008, at 08:17, Dave Liu wrote:
> Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
Applied, thanks
Andy
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On Oct 23, 2008, at 08:18, Dave Liu wrote:
> The 8572 DDR erratum1:
> DDR controller may enter an illegal state when operating
> in 32-bit bus mode with 4-beat bursts.
>
> Description:
> When operating with a 32-bit bus, it is recommended that
> DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories a
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Dave Liu (2):
85xx: remove unused config definition
85xx: Fix the incorrect register used for DDR erratum1
Kumar Gala (12):
85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic number
And thus have I done so. 1-10 applied, thanks
Andy
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On Thu, Oct 23, 2008 at 5:23 PM, Peter Tyser <[EMAIL PROTECTED]> wrote:
> Initial support for Extreme Engineering Solutions XPedite5370 -
> a MPC8572-based 3U VPX single board computer with a PMC/XMC
> site.
>
> Signed-off-by: Peter Tyser <[EMAIL PROTECTED]>
> ---
> MAINTAINERS
On Mon, Oct 27, 2008 at 2:22 PM, Peter Tyser <[EMAIL PROTECTED]> wrote:
> Signed-off-by: Peter Tyser <[EMAIL PROTECTED]>
> ---
> include/asm-ppc/immap_85xx.h |4
> 1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
On Mon, Oct 27, 2008 at 4:24 PM, Kumar Gala <[EMAIL PROTECTED]> wrote:
>
> On Oct 27, 2008, at 4:09 PM, Becky Bruce wrote:
>
>> The existing code has a few errors that need to be fixed in
>> order to support large RAM sizes. Fix those, and add a
>> comment to make it clearer.
>>
>> Signed-off-by:
On Mon, Oct 27, 2008 at 1:59 PM, Peter Tyser <[EMAIL PROTECTED]> wrote:
> Initial support for Extreme Engineering Solutions XPedite5370 -
> a MPC8572-based 3U VPX single board computer with a PMC/XMC
> site.
>
> Signed-off-by: Peter Tyser <[EMAIL PROTECTED]>
Ack
On Mon, Oct 27, 2008 at 1:16 PM, Kumar Gala <[EMAIL PROTECTED]> wrote:
> Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
Applied, thanks
Andy
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are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Andy Fleming (1):
Merge branch 'denx'
Becky Bruce (1):
powerpc: fix pci window initialization to work with > 4GB DRAM
Kumar Gala (1):
pci/fsl_pci_init: Removed a bunch point
On Mon, Oct 27, 2008 at 4:42 PM, Peter Tyser <[EMAIL PROTECTED]> wrote:
> The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx
> processors have a 3-bit wide IO_SEL field but have the most
> significant bit is wired to 0 so this change should not affect
> them.
>
> Signed-off-by: Peter
On Tue, Oct 28, 2008 at 4:53 AM, Dave Liu <[EMAIL PROTECTED]> wrote:
> The DDR controller of 8548/8544/8568/8572/8536 processors
> have the ECC data init feature, and the new DDR code is
> using the feature, and we don't need the way with DMA to
> init memory any more.
>
> Signed-off-by: Dave Liu <
On Tue, Oct 28, 2008 at 4:53 AM, Dave Liu <[EMAIL PROTECTED]> wrote:
> we need TLB entry for DDR at !SPD case.
>
> Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
Applied, thanks
Andy
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On Thu, Oct 30, 2008 at 12:53 AM, Ben Warren <[EMAIL PROTECTED]> wrote:
> This is no longer used by any boards, the last one was removed in
> commit 6de5bf24004c8d9c9b070bb8f7418d1c45e5eb27.
>
> Signed-off-by: Ben Warren <[EMAIL PROTECTED]>
Um8540ADS uses it. And the 8572 has one, even though
On Thu, Oct 30, 2008 at 3:30 PM, Andy Fleming <[EMAIL PROTECTED]> wrote:
> On Thu, Oct 30, 2008 at 12:53 AM, Ben Warren <[EMAIL PROTECTED]> wrote:
>> This is no longer used by any boards, the last one was removed in
>> commit 6de5bf24004c8d9c9b070bb8f7418d1c45e5eb2
Here's a new framework (based roughly off the linux one) for managing
MMC controllers. It handles all of the standard SD/MMC transactions,
leaving the host drivers to implement only what is necessary to
deal with their specific hardware.
We make a number of slow steps toward it before dropping it
There were several, now there is one (two if you count the lower-case
versions).
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
board/delta/nand.c |2 --
board/zylonite/nand.c |2 --
common/cmd_bedbug.c |4
common/cmd
These names are being taken over by the new MMC framework. Hopefuly
the PXA can be easily ported, and these functions will go away entirely.
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
cpu/pxa/mmc.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/c
stubs and the #include of asm/arch/mmc.h
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
cpu/pxa/mmc.c |2 +
cpu/pxa/mmc.h | 189 +++
include/asm-arm/arch-lpc2292/mmc.h | 22
include/asm-a
This uses the new MMC framework
Some contributions by Dave Liu <[EMAIL PROTECTED]>
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
drivers/mmc/Makefile|1 +
drivers/mmc/fsl_esdhc.c | 344 +++
include/fsl_esdhc.
This is to get it out of the way of incoming MMC framework
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
common/cmd_mmc.c |2 +-
cpu/arm720t/lpc2292/mmc.c |4 ++--
cpu/pxa/mmc.c |2 +-
drivers/mmc/atmel_mci.c |2 +-
include/mmc.h
From: Dave Liu <[EMAIL PROTECTED]>
Current fat.c have three 64KB static array, it makes the BSS section larger.
Change the static to dynamic allocation.
Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
---
fs/fat/fat.c | 38 +++---
1 files changed, 35 insertions(+),
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
board/freescale/mpc8536ds/mpc8536ds.c | 12
cpu/mpc85xx/cpu.c | 16 +++-
include/configs/MPC8536DS.h | 14 ++
3 files changed, 41 insertions(+), 1 deletions(-)
diff
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
board/freescale/mpc837xemds/mpc837xemds.c | 19 +++
cpu/mpc83xx/cpu.c | 14 ++
include/asm-ppc/immap_83xx.h |2 ++
include/configs/MPC837XEMDS.h
MMC cards are not memory, so we stop treating them that way.
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
common/cmd_mem.c | 43 ---
cpu/arm720t/lpc2292/mmc.c | 26 --
cpu/pxa/mmc.c
board code
(similar to how the ethernet infrastructure now hooks in)
Some of this code was contributed by Dave Liu <[EMAIL PROTECTED]>
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
common/cmd_mmc.c | 122 +++
drivers/mmc/Makefile |1 +
drivers/mm
On Fri, Oct 31, 2008 at 12:22 AM, Ben Warren <[EMAIL PROTECTED]> wrote:
> CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC
>
> Signed-off-by: Ben Warren <[EMAIL PROTECTED]>
Applied, thanks
Andy
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On Tue, Nov 4, 2008 at 3:37 AM, Haavard Skinnemoen
<[EMAIL PROTECTED]> wrote:
> Andy Fleming <[EMAIL PROTECTED]> wrote:
>> + mmc_init(mmc);
>> +
>> + n = mmc->block_dev.block_write(dev, blk, cnt, addr);
>> +
>>
On Tue, Nov 25, 2008 at 12:31 PM, Ben Warren <[EMAIL PROTECTED]> wrote:
> Hi Michal,
> Michal Simek wrote:
>> Hi Ben,
>>
>> how does look like your propose work about PHY lib?
>>
>> Thanks,
>> Michal
>>
>>
> I'd like to have the PHY library included in the 02.2009 release. One
> of the things I'm
istered phy 1 interrupt
> handler doesn't acknowledge phy 0 interrupts. This
> of course should be fixed in Linux driver too.
Agreed, and...
>
> Signed-off-by: Anatolij Gustschin <[EMAIL PROTECTED]>
Acked-by: Andy Fleming <[EMAIL PROTECTED]>
_
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE1; /* disable */
+#endif /* CONFIG_PCIE2 */
MPC85xx_DEVDISR_PCIE1 isn't defined anywhere. Did you miss some
changes you made to header files?
Andy
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are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Anatolij Gustschin (1):
85xx: socrates: fix DDR SDRAM tlb entry configuration
Becky Bruce (1):
drivers/fsl_pci_init: Fix inbound window mapping bug
Dave Liu (3):
85xx: remove the unused d
On Fri, Nov 21, 2008 at 2:31 AM, Dave Liu <[EMAIL PROTECTED]> wrote:
> According to the latest 8572 UM, the DDR3 controller
> is expanding the bit mask, and we use the extend ACTTOPRE
> mode when tRAS more than 19 MCLK.
>
> Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
Applied to 85xx-next, thanks
On Thu, Nov 20, 2008 at 3:36 PM, Jon Loeliger <[EMAIL PROTECTED]> wrote:
> Prevent further viral propogation of the unused
> symbol CONFIG_L1_INIT_RAM by just removing it.
>
> Signed-off-by: Jon Loeliger <[EMAIL PROTECTED]>
Applied, thanks
Andy
___
U-Bo
On Wed, Oct 29, 2008 at 8:21 AM, Ed Swarthout
<[EMAIL PROTECTED]> wrote:
> Removed while(1) hang if memctl_intlv_ctl is set wrong.
> Remove embedded tabs from strings.
>
> Signed-off-by: Ed Swarthout <[EMAIL PROTECTED]>
Applied, thanks
Andy
___
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> This patch makes the presence of the DDR SDRAM tlb entry in
> the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this
> inconsistency.
>
> Signed-off-by: Anatolij Gustschin <[EMAIL PROTECTED]>
Applied, thanks
Andy
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On Tue, Nov 11, 2008 at 7:52 AM, Haiying Wang
<[EMAIL PROTECTED]> wrote:
>
> Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
Applied to 85xx-next, thanks
Andy
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On Tue, Nov 11, 2008 at 10:17 AM, Peter Tyser <[EMAIL PROTECTED]> wrote:
> All mpc8548-based boards should implement the suggested workaround
> to CPU 2 errata. Without the workaround, its possible for the
> 8548's core to hang while executing a msync or mbar 0 instruction
> and a snoopable transac
On Mon, Dec 1, 2008 at 1:47 PM, Peter Tyser <[EMAIL PROTECTED]> wrote:
> Add define used to determine if PCI1 interface is in PCI or PCIX mode.
>
> Signed-off-by: Peter Tyser <[EMAIL PROTECTED]>
I thought this already had a constant defined, and I was right. It
was PORDEVSR_PCI. However, it wasn
On Fri, Nov 21, 2008 at 2:31 AM, Dave Liu <[EMAIL PROTECTED]> wrote:
> For light loaded system, we use the 1T timing to gain better
> memory performance, but for some heavily loaded system,
> you have to add the 2T timing options to board files.
>
> Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
Appl
On Fri, Nov 21, 2008 at 2:31 AM, Dave Liu <[EMAIL PROTECTED]> wrote:
> The wake up ARP feature need use the memory to process
> wake up packet, we enable auto self refresh to support it.
>
> Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
Applied to 85xx-next, thanks
__
On Fri, Nov 21, 2008 at 2:31 AM, Dave Liu <[EMAIL PROTECTED]> wrote:
> - The DDR3 controller is expanding the bits for timing config
> - Add the DDR3 32-bit bus mode support
>
> Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
Applied to 85xx-next, thanks
___
On Fri, Nov 21, 2008 at 2:31 AM, Dave Liu <[EMAIL PROTECTED]> wrote:
> According to the latest 8572 UM, the DDR3 controller
> is expanding the bit mask, and we use the extend ACTTOPRE
> mode when tRAS more than 19 MCLK.
>
> Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
Applied to 85xx-next, thanks
_
On Fri, Nov 21, 2008 at 2:31 AM, Dave Liu <[EMAIL PROTECTED]> wrote:
> Some 85xx processors have the advanced power management feature,
> such as wake up ARP, that needs enable the automatic self refresh.
>
> If the DDR controller pass the SR_IT (self refresh idle threshold)
> idle cycles, it will
On Fri, Nov 21, 2008 at 7:24 PM, <[EMAIL PROTECTED]> wrote:
> From: Becky Bruce <[EMAIL PROTECTED]>
>
> The current code will cause the creation of a 4GB window
> starting at 0 if we have more than 4GB of RAM installed,
> which overlaps with PCI_MEM space and causes pci_bus_to_phys()
> to return e
ce. It also makes it explicitly clear that
> the generic PHY must be last in the PHY table.
>
> Signed-off-by: Paul Gortmaker
Acked-by: Andy Fleming
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are available in the git repository at:
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Jon Loeliger (5):
FSL DDR: Convert MPC8560ADS to new DDR code.
FSL DDR: Convert MPC8555ADS to new DDR code.
FSL DDR: Convert MPC8541CDS to new DDR code.
FSL DDR: Convert MPC8548CDS to
This is to prepare the way for board code passing in the tsec_info structure
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
drivers/net/tsec.c |8 +---
{drivers/net => include}/tsec.h |6 ++
2 files changed, 7 insertions(+), 7 deletions(-)
rename {dr
SGMII PHYs on the card, instead.
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
board/freescale/common/Makefile |1 +
board/freescale/common/sgmii_riser.c | 26 ++
board/freescale/common/sgmii_riser.h | 15 +++
include/configs/MPC85
Adds support for configuring the TBI to talk properly with the SerDes.
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
drivers/net/tsec.c | 74 +--
include/tsec.h | 25 +-
2 files changed, 72 insertions(+), 27 del
ctures, which are then parsed by the corresponding
driver instance to determine configuration. Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
not work on the 8572, as the PIXIS is different.
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
board/freescale/common/pixis.c | 55
include/configs/MPC8544DS.h|5 +++
2 files changed, 60 insertions(+), 0 deletions(-)
diff --git a
The 8544 DS has an optional SGMII Riser card, which uses different PHY
addresses. Check if we are in SGMII mode, and invoke the SGMII Riser
setup code if so.
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
board/freescale/mpc8544ds/mpc8544ds.c | 39 ++
On Sat, Sep 6, 2008 at 6:38 PM, Wolfgang Denk <[EMAIL PROTECTED]> wrote:
> Dear Andy,
>
> I have a couple of unapplied patches in my list which seem to fall
> into your area of responsibility. Can you please have a look at
> these:
Yes, I'm currently trying to churn through my u-boot backlog (OLS,
On Tue, Sep 2, 2008 at 2:37 PM, Nícolas Carneiro Lebedenco
<[EMAIL PROTECTED]> wrote:
> Hi,
>
> I'm developing a custom board based on the AT91RM9200dk. In u-boot prompt,
> every time a enter a network command such as tftp or ping I get a message
> like this:
>
> "MAC: error during MII initializati
On Mon, Sep 1, 2008 at 8:57 AM, Detlev Zundel <[EMAIL PROTECTED]> wrote:
> That's really nice that we get the socrates board converted to the new
> style DDR, but I wonder why the other patches for socrates([1]-[3]) are
> becoming neglected pets of myself instead of moving on. Can you please
> co
On Wed, Aug 27, 2008 at 12:16 AM, Ajeesh Kumar <[EMAIL PROTECTED]> wrote:
> hi sir/madam,
>
> I'm using a MPC8548E processor(power pc) also, i've interfaced a nor flash
> of 128 MB to the processor.
> i've read few documents and got to know that the uboot.bin should be
> programmed at 0xfff8.
>
On Mon, Sep 8, 2008 at 6:39 PM, Peter Tyser <[EMAIL PROTECTED]> wrote:
> The original code only supported using 1 TSEC port in SGMII mode using an
> internal TBI PHY. Additionally, the TBI internal PHY was being accessed
> at the same register offset as the external PHY for the given TSEC port.
>
board_show_activity(). I'll leave it to the stx* maintainer to
implement that function if desired. :)
Signed-off-by: Andy Fleming <[EMAIL PROTECTED]>
---
include/configs/stxgp3.h |4
include/configs/stxssa.h |4
2 files changed, 0 insertions(+), 8 deletions(-)
diff --git a/incl
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Anatolij Gustschin (1):
85xx: socrates: Enable Lime support.
Andy Fleming (1):
Remove CONFIG_SHOW_ACTIVITY from stx boards which don't support it
Detlev Zundel (1):
85xx: Socrates:
On Tue, Sep 9, 2008 at 3:15 PM, Kumar Gala <[EMAIL PROTECTED]> wrote:
>> I NAK the CONFIG_SHOW_ACTIVITY patch. Please remove this from your
>> repo. Please see my "[PATCH 3/3] lib_ppc/interrupts.c: make
>> board_show_activity() a weak function" posting instead.
>>
>> I cherry-picked the other comm
On Mon, Sep 8, 2008 at 8:51 AM, Kumar Gala <[EMAIL PROTECTED]> wrote:
> The e500um says the timebase is volatile out of reset. To ensure
> TB sync works we need to make sure its zero.
>
> Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
> ---
> Swapped mftbl,mftbu at Scott's request.. it doesnt mater
On Thu, Aug 21, 2008 at 9:12 AM, Andrew Klossner
<[EMAIL PROTECTED]> wrote:
> Fix printf format-string/arg mismatches under -DDEBUG.
>
> These warnings occur with DEBUG defined for a platform using
> cpu/mpc85xx. Users of other architectures can unearth similar
> problems by adding the line "CFLAG
On Sat, Sep 6, 2008 at 6:38 PM, Wolfgang Denk <[EMAIL PROTECTED]> wrote:
> Dear Andy,
>
> I have a couple of unapplied patches in my list which seem to fall
> into your area of responsibility. Can you please have a look at
> these:
>
> 4316 07/18 Timur Tabi [U-Boot-Users] [PATCH] Update F
):
85xx: socrates: Enable Lime support.
Andy Fleming (1):
Merge branch 'denx'
Detlev Zundel (1):
85xx: Socrates: Major code update.
Sergei Poselenov (1):
Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.
Timur Tabi (1):
Update Freescale 85xx
> @@ -299,12 +301,10 @@ static int init_phy(struct eth_device *dev)
> {
>struct tsec_private *priv = (struct tsec_private *)dev->priv;
>struct phy_info *curphy;
> - volatile tsec_t *phyregs = priv->phyregs;
>volatile tsec_t *regs = priv->regs;
>
>/* Assign a P
On Mon, Sep 15, 2008 at 5:17 PM, Peter Tyser <[EMAIL PROTECTED]> wrote:
> On Mon, 2008-09-15 at 16:13 -0500, Andy Fleming wrote:
>> > @@ -299,12 +301,10 @@ static int init_phy(struct eth_device *dev)
>> > {
>> >struct tsec_private *pri
> According to the 8548 and 8572 manuals (not sure about others...), the
> TBIPA register value for all PHYs is 0x0 at reset, which is reserved
> according to the manuals. The description of the MIIMADD register
> supports this by stating: "Up to 31 PHYs can be addressed (0 is
> reserved)". So I
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Peter Tyser (1):
Support for multiple SGMII/TBI interfaces for TSEC ethernet
drivers/net/tsec.c |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
_
On Mon, Sep 22, 2008 at 3:33 PM, Andrew Dyer <[EMAIL PROTECTED]> wrote:
> On Mon, Sep 22, 2008 at 3:11 PM, Wolfgang Denk <[EMAIL PROTECTED]> wrote:
>> Dear Stefan, Kim, Andy, Jon & Kumar,
>>
>> in message <[EMAIL PROTECTED]>
>> Nobuhiro Iwamatsu wrote:
>>>
>>> I did a simple check.
>>>
>>> Only pow
From: Haiying Wang <[EMAIL PROTECTED]>
Change UEC phy interface from GMII to RGMII on MPC8568MDS board
Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed,
but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more
stable.
Now both UEC1 and UEC2 can
On Tue, Sep 30, 2008 at 11:27 AM, Anton Vorontsov
<[EMAIL PROTECTED]> wrote:
> We'll need the exported tsec_info to fix up the phy addresses and
> tsecs' flags based on the hardware reset configuration words. Thus
> we'll use the tsec_info very early and just once at boot time, so
> network code wo
If Kim and Jon approve, I'll pull these 6 patches into my 85xx-next branch.
On Fri, Oct 3, 2008 at 11:36 AM, Haiying Wang
<[EMAIL PROTECTED]> wrote:
> Fix some bugs:
> 1. Correctly set intlv_ctl in cs_config.
> 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
> 3. Set
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Haiying Wang (3):
Minor fixes for I2C address on MPC8572DS
Add ID EEPROM support for MPC8572DS
Remove redundant #define for MPC8536DS
Jason Jin (1):
Fix the incorrect DDR clk freq re
TA
> initialize.
>
> Signed-off-by: Jason Jin <[EMAIL PROTECTED]>
Acked-by: Andy Fleming <[EMAIL PROTECTED]>
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are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
This supercedes the previous pull request. This includes Wolfgang's and Kumar's
patches.
Haiying Wang (3):
Minor fixes for I2C address on MPC8572DS
Add ID EEPROM support for MPC8572DS
Rem
The following changes since commit 53237afe5b64abe7b17fbfed958f3dc83f503ffa:
cmd_mem: fix cp command (2013-05-24 10:38:08 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
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