On Tue, Nov 11, 2008 at 10:17 AM, Peter Tyser <[EMAIL PROTECTED]> wrote: > All mpc8548-based boards should implement the suggested workaround > to CPU 2 errata. Without the workaround, its possible for the > 8548's core to hang while executing a msync or mbar 0 instruction > and a snoopable transaction from an I/O master tagged to make > quick forward progress is present. > > Signed-off-by: Peter Tyser <[EMAIL PROTECTED]>
Applied, thanks Andy _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
