From: Wang Huan
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang
---
Change log:
v6: No change.
v5: Change the patch order.
v4: Add commit messages.
v3: New file.
board/freescale/common/Mak
high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: Jing
From: Alison Wang
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.
Signed-off-by: Alison Wang
---
Change log:
v6: Fix checkpatch error.
v5: No change.
v4: No change.
v3: Use mb() to be compatible for both ARM and PowerPC.
Split from the 0004-arm
From: Wang Huan
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang
---
Change log:
v6: Use #define instead of magic numbers.
v5: Change the patch order.
v4: Add commit messages.
v3: New file.
board
From: Jingchang Lu
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu
Signed-off-by: Yuan Yao
---
Change log:
v6: Fix the influence to other board.
v5: No change.
v4: Ad
From: York Sun
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun
---
Change log:
v6: No change.
v5: No change.
v4: No change.
v3: No change.
v2: No change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2
From: Alison Wang
This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.
Signed
From: York Sun
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
---
Change log:
v6: No cha
From: York Sun
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to us
From: Wang Huan
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang
---
Change log:
v6
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR
board.
The QorIQ LS1 family is built on Layerscape architecture, the industry's first
software-aware, core-agnostic networking architecture to offer unprecedented
efficiency and scale.
Freescale LS102xA is a set of SoCs
From: Claudiu Manoil
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To
-by: Alison Wang
---
Change log:
v6: Make the commit more clear.
Split from the v5' 06 patch.
v5: No change.
v4: No change.
v3: Add commit messages.
v2: No change.
drivers/mmc/fsl_esdhc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/fsl_esdh
From: Wang Huan
For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.
Signed-off-by: Alison Wang
---
Change log
From: Wang Huan
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: York
From: Claudiu Manoil
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot be reset from Linux, for inst
From: Wang Huan
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu
Signed-off-by: Yuan Yao
Signed-off-by: Alison Wang
In SD boot, the magic number of u-boot image will be checked.
For LS102xA, u-boot.bin doesn't have the magic number. So use
u-boot.img which includes the magic number instead of u-boot.bin
when building u-boot-with-spl-pbl.bin.
Signed-off-by: Alison Wang
---
Makefile | 4 +++-
1 file chang
spl/u-boot-spl-pbl-pad.bin is built, and the size of
it is a fixed value "CONFIG_SPL_MAX_SIZE". Use it instead of
spl/u-boot-spl.bin for LS102xA.
CONFIG_SPL_PBL_PAD is used to enable this function.
Signed-off-by: Alison Wang
---
Makefile | 17 -
1 file changed, 16 insert
.
Signed-off-by: Alison Wang
---
tools/pblimage.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/tools/pblimage.c b/tools/pblimage.c
index 6e6e801..152678b 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -12,6 +12,10 @@
* Initialize to an invalid
.
Alison Wang (7):
spl: pbl: Add new SPL image for pblimage tool
ls102xa: pblimage: Add pblimage tool support for LS102xA
spl: Use u-boot.img instead of u-boot.bin when CONFIG_SPL_PBL_PAD is
enabled
ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macro
common
Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.
Signed-off-by: Jason Jin
Signed-off-by: Alison Wang
---
board/freescale/common/qixis.h | 7 +++
1 file changed, 7
For LS102xA, interactive DDR debugger is still needed in SPL part.
So build the needed files in SPL image too.
Signed-off-by: Alison Wang
---
common/Makefile | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/common/Makefile b/common/Makefile
index aca0f7f
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Chen Lu
Signed-off-by: Alison Wang
Hi, Albert,
On Thu, 18 Sep 2014 13:47:18 +0800, Alison Wang
wrote:
> +
> + . = ALIGN(4);
> + .u_boot_list : {
> + KEEP(*(SORT(.u_boot_list*_i2c_*)));
> + }
IS this required? And if it is, could it not be added to the
arch/arm/cpu/u-boot-spl.lds file? Thi
For LS102xA, interactive DDR debugger is still needed in SPL part.
So build the needed files in SPL image too.
Signed-off-by: Alison Wang
---
Change log:
v2: No change.
common/Makefile | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/common/Makefile b
.
Alison Wang (7):
ls102xa: pblimage: Add pblimage tool support for LS102xA
spl: Use u-boot.img instead of u-boot.bin
arm: spl: Add I2C linker list in generic .lds
common: spl: Add interactive DDR debugger support for SPL
ls102xa: qixis: Add
calculation
of pbl_cmd_initaddr.
Signed-off-by: Alison Wang
---
Change log:
v2: Remove the definition of CONFIG_SPL_MAX_SIZE.
Pad the variable u-boot size to 64 byte boundary in pblimage tool.
Use pblimage_check_params() insteady of basing on the file name.
Makefile | 3 +-
tools
Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.
Signed-off-by: Jason Jin
Signed-off-by: Alison Wang
---
Change log:
v2: No change.
board/freescale/common/qixis.h
In SD boot, the magic number of u-boot image will be checked.
For LS102xA, u-boot.bin doesn't have the magic number. So use
u-boot.img which includes the magic number instead of u-boot.bin
when producing u-boot-with-spl-pbl.bin.
Signed-off-by: Alison Wang
---
Change log:
v2: No c
to fix the issue about
using I2C in SPL.
Signed-off-by: Alison Wang
---
Change log:
v2: New file.
arch/arm/cpu/u-boot-spl.lds | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index 4beddf0..bddef74 100644
--- a/arch/arm/cpu/u-boot
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Chen Lu
Signed-off-by: Alison Wang
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
From: Jason Jin
Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.
Signed-off-by: Jason Jin
Signed-off-by: Minghuan Lian
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
board/freescale/ls1021aqds/ls1021aqds.c | 7 +++
boa
y.
Signed-off-by: Alison Wang
---
board/freescale/ls1021aqds/ls1021aqds.c | 2 --
board/freescale/ls1021atwr/ls1021atwr.c | 5 -
2 files changed, 7 deletions(-)
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index e32dbeb..56028f8 100644
-
From: Yuan Yao
Add define CONFIG_SYS_WRITE_SWAPPED_DATA.
For LS1021AQDS and LS1021QTWR nor flash read and write should swap the
bytes when handle unaligned tail bytes.
Signed-off-by: Yuan Yao
---
include/configs/ls1021aqds.h | 1 +
include/configs/ls1021atwr.h | 1 +
2 files changed, 2 inserti
SystemID information could be read through I2C1 from EEPROM
on LS1021ATWR board.
As LS1 is a little-endian processor, getting the version ID by
be32_to_cpu() is wrong. Fix it by using e.version directly.
This change will be compatible for both ARM and PowerPC.
Signed-off-by: Alison Wang
y.
Signed-off-by: Alison Wang
---
Change log:
v2: Remove the defines for SCFG_SCFGREVCR_REV and
SCFG_SCFGREVCR_NOREV.
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 --
board/freescale/ls1021aqds/ls1021aqds.c | 2 --
board/freescale/ls1021atwr/ls1021atwr.c | 5
From: Jason Jin
Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.
Signed-off-by: Jason Jin
Signed-off-by: Minghuan Lian
---
Change log:
v2: Add tag "arm: ls102xa:" in the subject.
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
board/fre
From: Yuan Yao
Add define CONFIG_SYS_WRITE_SWAPPED_DATA.
For LS1021AQDS and LS1021QTWR nor flash write should swap the
bytes when handle unaligned tail bytes.
Because of the ending, if the date bus width is 16-bits and the
number of bytes is odd, we should swap the byte when write the
last one.
EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or
SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1
as other functionality except RGMII. The workaround is to select
ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR.
Signed-off-by: Alison Wang
could not work in SD boot,
reading EEPROM through I2C1 is disabled too in SD boot.
Signed-off-by: Alison Wang
---
Change log:
v2: Add the compatibility in SD boot.
board/freescale/common/sys_eeprom.c | 4 ++--
include/configs/ls1021atwr.h| 11 +++
2 files changed, 13 insertions
definition of CONFIG_SPL_MAX_SIZE.
Pad the variable u-boot size to 64 byte boundary in pblimage tool.
Use pblimage_check_params() insteady of basing on the file name.
Use generic u-boot-spl.lds.
Alison Wang (8
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
In SD boot, the magic number of u-boot image will be checked.
For LS102xA, u-boot.bin doesn't have the magic number. So use
u-boot.img which includes the magic number instead of u-boot.bin
when producing u-boot-with-spl-pbl.bin.
Signed-off-by: Alison Wang
---
Change log:
v3: No change.
v
to fix the issue about
using I2C in SPL.
Signed-off-by: Alison Wang
---
Change log:
v3: No change.
v2: New file.
arch/arm/cpu/u-boot-spl.lds | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index 4beddf0..bddef74 100644
--- a
calculation
of pbl_cmd_initaddr.
Signed-off-by: Alison Wang
---
Change log:
v3: Change the Copyright year.
v2: Remove the definition of CONFIG_SPL_MAX_SIZE.
Pad the variable u-boot size to 64 byte boundary in pblimage tool.
Use pblimage_check_params() insteady of basing on the file name
Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.
Signed-off-by: Jason Jin
Signed-off-by: Alison Wang
---
Change log:
v3: No change.
v2: No change.
board/freescale
ot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2
So this patch fixed this issue and the above .o files will be produced
no matter CONFIG_SPL_BUILD is enabled or disabled.
Signed-off-by: Alison Wang
---
Change log:
v3: Gave more explaination in the commit.
v2: No change.
commo
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Chen Lu
Signed-off-by: Alison Wang
: Alison Wang
---
Change log:
v3: New file.
arch/arm/include/asm/arch-ls102xa/config.h| 1 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +
board/freescale/ls1021aqds/MAINTAINERS| 1 +
board/freescale/ls1021aqds/ls1021aqds.c | 16 ++
board/freescale
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
This patch is based on the previous QSPI enabled patches.
Signed-off-by: Alison Wang
---
board/freescale
l and general purpose applications.
Alison Wang (5):
vybrid: add vybrid CPU support
vybrid: add Freescale vybrid vf600 tower board support
vybrid: add uart driver support
vybrid: add eSDHC driver support
vybrid: add ethernet driver support
Mak
This patch adds Freescale vybrid vf600 tower board support.
Signed-off-by: TsiChung Liew
Signed-off-by: Jason Jin
Signed-off-by: Alison Wang
---
board/freescale/vybrid/Makefile| 40 +++
board/freescale/vybrid/vybrid.c| 488 +
board/freescale
This patch uses the general ffs definition to replace the
platform ffs definition.
This patch also fixes the build error by adding hweightN
definition for m5329evb and m5373evb.
Signed-off-by: Jason Jin
Signed-off-by: Alison Wang
---
arch/m68k/include/asm/bitops.h | 59
This patch fixes the build error for MCF537x. As the NANDFLASH_SIZE is
redefined in boards.cfg, it is needed to rename NANDFLASH_SIZE into
CONFIG_NANDFLASH_SIZE in include/configs/M5373EVB.h.
Signed-off-by: Alison Wang
---
include/configs/M5373EVB.h | 10 +-
1 files changed, 5
From: Alison Wang
This patch cleans up checkpatch warnings about "Use of volatile is usually
wrong"
for ColdFire platform.
The first patch adds clear and set bits macros for ColdFire platform. These
macros can be used to clear and set multiple bits in a register using a
single c
Signed-off-by: Alison Wang
---
arch/m68k/cpu/mcf5227x/cpu.c | 13 ++--
arch/m68k/cpu/mcf5227x/cpu_init.c | 140 +
arch/m68k/cpu/mcf5227x/interrupts.c | 15 ++--
arch/m68k/cpu/mcf5227x/speed.c| 40 +-
board/freescale/m52277evb
Signed-off-by: Alison Wang
---
arch/m68k/cpu/mcf52x2/cpu.c | 115 +--
arch/m68k/cpu/mcf52x2/cpu_init.c | 252 +
arch/m68k/cpu/mcf52x2/interrupts.c| 40 +++---
arch/m68k/cpu/mcf52x2/speed.c | 19 ++--
board/freescale
Signed-off-by: Alison Wang
---
arch/m68k/cpu/mcf5445x/cpu.c | 13 +-
arch/m68k/cpu/mcf5445x/cpu_init.c | 215 +
arch/m68k/cpu/mcf5445x/interrupts.c | 15 ++-
arch/m68k/cpu/mcf5445x/pci.c | 74 ++--
arch/m68k/cpu/mcf5445x
Signed-off-by: Alison Wang
---
arch/m68k/cpu/mcf547x_8x/cpu.c| 38 +++---
arch/m68k/cpu/mcf547x_8x/cpu_init.c | 84 +
arch/m68k/cpu/mcf547x_8x/interrupts.c | 15 +++---
arch/m68k/cpu/mcf547x_8x/pci.c| 59
Signed-off-by: Alison Wang
---
arch/m68k/cpu/mcf532x/cpu.c | 33 ++--
arch/m68k/cpu/mcf532x/cpu_init.c | 304 +
arch/m68k/cpu/mcf532x/interrupts.c| 15 +-
arch/m68k/cpu/mcf532x/speed.c | 77 +
board/freescale/m53017evb
Signed-off-by: Alison Wang
---
arch/m68k/include/asm/io.h | 38 +-
1 files changed, 37 insertions(+), 1 deletions(-)
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
index d86eaf9..50ed749 100644
--- a/arch/m68k/include/asm/io.h
+++ b
Signed-off-by: Alison Wang
---
arch/m68k/cpu/mcf523x/cpu.c | 33 +
arch/m68k/cpu/mcf523x/cpu_init.c| 122 ++-
arch/m68k/cpu/mcf523x/interrupts.c | 15 ++--
arch/m68k/cpu/mcf523x/speed.c | 10 ++-
board/freescale/m5235evb
This patch adds eSDHC driver support for vybrid platform.
Signed-off-by: TsiChung Liew
Signed-off-by: Jason Jin
Signed-off-by: Alison Wang
---
drivers/mmc/fsl_esdhc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
This patch adds uart driver support for vybrid platform.
Signed-off-by: TsiChung Liew
Signed-off-by: Jason Jin
Signed-off-by: Alison Wang
---
drivers/serial/Makefile| 1 +
drivers/serial/serial.c| 2 +
drivers/serial/serial_vybrid.c | 129
This patch adds ethernet driver support for vybrid platform.
Signed-off-by: TsiChung Liew
Signed-off-by: Jason Jin
Signed-off-by: Alison Wang
---
arch/arm/include/asm/fec.h| 302 ++
arch/arm/include/asm/u-boot.h | 3 +
drivers/net/mcffec.c
;mvf600twr'
- Use standard method to set gd->ram_size
- Rewrite board_mmc_getcd() function
- Remove useless undef
- Remove hardcoded IP addresses and MAC addresses
- Move CONFIG_MACH_TYPE to board configuration file
----
Alison Wang
This patch adds generic codes to support Freescale's Vybrid MVF600 CPU.
It aligns Vybrid MVF600 platform with i.MX platform. As there are
some differences between MVF600 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/mvf600 directory.
Signed-off-by: Alison Wang
---
Ch
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
Signed-off-by: Alison Wang
---
Changes in v2:
- Use common iomux-v3 code
arch/arm/imx-common/Makefile | 2 +-
arch/arm/imx-common/iomux-v3.c | 6 ++
arch/arm/include/asm/imx-common/iomux-v3.h | 18 ++
3
This patch adds FEC support for Vybrid MVF600 platform.
Add code to use RMII for MVF600.
Signed-off-by: Alison Wang
---
Changes in v2:
- Use common FEC driver fec_mxc.c
drivers/net/fec_mxc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/fec_mxc.c b
This patch adds watchdog support for Vybrid MVF600 platform.
Signed-off-by: Alison Wang
---
Changes in v2:
- Add watchdog support
- Use reset_cpu() in imx_watchdog.c
drivers/watchdog/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/Makefile b
This patch adds lpuart support for Vybrid MVF600 platform.
Signed-off-by: TsiChung Liew
Signed-off-by: Alison Wang
---
Changes in v2:
- Define C structures and access C structures to set/read registers
- Change the names to reuse this driver on other platforms
drivers/serial/Makefile
MVF600TWR is a board based on Vybrid MVF600 SoC.
This patch adds basic support for Vybrid MVF600TWR board.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: TsiChung Liew
---
Changes in v2:
- Add an entry to MAINTAINERS file
- Rename directory name 'vybird' to
This patch adds watchdog support for Vybrid MVF600 platform.
Signed-off-by: Alison Wang
---
Changes in v3: None
Changes in v2:
- Add watchdog support
- Use reset_cpu() in imx_watchdog.c
drivers/watchdog/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
Signed-off-by: Alison Wang
---
Changes in v3:
- Define PAD_CTL_PUE with PKE enabled
Changes in v2:
- Use common iomux-v3 code
arch/arm/imx-common/Makefile | 2 +-
arch/arm/imx-common/iomux-v3.c | 6 ++
arch/arm/include
This patch adds lpuart support for Vybrid MVF600 platform.
Signed-off-by: TsiChung Liew
Signed-off-by: Alison Wang
---
Changes in v3:
- Move the structure definition to imx-regs.h
Changes in v2:
- Define C structures and access C structures to set/read registers
- Change the names to reuse
dard method to set gd->ram_size
- Rewrite board_mmc_getcd() function
- Remove useless undef
- Remove hardcoded IP addresses and MAC addresses
- Move CONFIG_MACH_TYPE to board configuration file
----
Alison Wang (6):
arm: mvf600:
FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang
---
Changes in v3:
- Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits, as they are already set in fec_reg_setup()
Changes in v2:
- Use common FEC driver fec_mxc.c
drivers
MVF600TWR is a board based on Vybrid MVF600 SoC.
This patch adds basic support for Vybrid MVF600TWR board.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: TsiChung Liew
---
Changes in v3:
- Replace BOOT_FROM by BOOT_OFFSET
- Enable CONFIG_OF_LIBFDT option
- Add useful
This patch adds generic codes to support Freescale's Vybrid MVF600 CPU.
It aligns Vybrid MVF600 platform with i.MX platform. As there are
some differences between MVF600 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/mvf600 directory.
Signed-off-by: Alison Wang
---
Ch
Signed-off-by: Alison Wang
---
drivers/i2c/mxc_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 48468d7..792fc40 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -423,7 +423,7 @@ static void * const
Signed-off-by: Alison Wang
---
drivers/net/fsl_mdio.c | 15 ---
drivers/net/tsec.c | 7 +++
include/tsec.h | 7 ++-
3 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 8d09f5d..5cee709 100644
From: York Sun
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to us
From: York Sun
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
---
drivers/ddr/fsl/ctrl_r
From: York Sun
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun
---
drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/fsl/arm_ddr_gen3
etail information about LS1021AQDS board, please refer to README in
the patch.
Alison Wang (5):
arm: ls102xa: Add Freescale LS102xA SoC support
arm: ls102xa: Add i2c support for LS102xA
arm: ls102xa: Add etsec suppor
y and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: Jingchang Lu
Signed-o
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: York Sun
Signed-off-by: Yuan Yao
Signed-off-by: Prabhakar Kushwaha
---
board/freescale/ls1021aqds/Makefile | 8 +
board/freescale/ls1021aqds/README | 112 +++
board/freescale/ls1021aqds/ddr.c
From: Claudiu Manoil
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To
Signed-off-by: Alison Wang
---
drivers/mmc/fsl_esdhc.c | 4 ++--
include/fsl_esdhc.h | 14 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 5541613..aec459f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b
Signed-off-by: Alison Wang
---
Change log:
v2: Add private mdio read and write support.
drivers/net/fsl_mdio.c | 24 +++-
drivers/net/tsec.c | 7 +++
include/fsl_mdio.h | 3 +++
include/tsec.h | 7 ++-
4 files changed, 35 insertions(+), 6
y and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: Jingchang Lu
Signed-o
Signed-off-by: Alison Wang
---
Change log:
v2: no change.
drivers/mmc/fsl_esdhc.c | 4 ++--
include/fsl_esdhc.h | 14 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 5541613..aec459f 100644
--- a
From: Claudiu Manoil
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR
board.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
From: York Sun
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
---
Change log:
v2: no cha
Signed-off-by: Yuan Yao
Signed-off-by: Alison Wang
---
Change log:
v2: New file.
board/freescale/ls1021atwr/Makefile | 7 +
board/freescale/ls1021atwr/README | 109 +++
board/freescale/ls1021atwr/ls1021atwr.c | 499
boards.cfg
From: York Sun
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to us
101 - 200 of 370 matches
Mail list logo
