Hi Jens,
Am 19.01.24 um 22:26 schrieb Jens Maus:
Hi,
Am 19.01.2024 um 17:53 schrieb Jens Maus :
Am 19.01.2024 um 17:29 schrieb Ivan T. Ivanov :
So you say with your own u-boot.bin you see serial U-Boot output after that
„NOTICE: BL31: …“ lines? On that special UART port on the rpi5 or on
Hi,
> Am 20.01.2024 um 10:22 schrieb Stefan Wahren :
>
> Am 19.01.24 um 22:26 schrieb Jens Maus:
>> I actually do have some good and bad news:
>>
>> 1. Good news: I got u-boot finally showing up with my RaspberryPi5 8GB both
>> on the HDMI and on the serial debug UART like you reported.
>>
>>
Hi,
Am 20.01.24 um 10:48 schrieb Jens Maus:
Hi,
Am 20.01.2024 um 10:22 schrieb Stefan Wahren :
Am 19.01.24 um 22:26 schrieb Jens Maus:
I actually do have some good and bad news:
1. Good news: I got u-boot finally showing up with my RaspberryPi5 8GB both on
the HDMI and on the serial debug
Cool Pi CM5 EVB works as a mother board connect with CM5.
CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S
CM5 EVB Specification:
- HDMI Ty
CoolPi 4B is a rk3588s based SBC.
Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT mod
On Fri, Jan 19, 2024 at 1:08 PM Marek Vasut wrote:
>
> The CONFIG_SPL_BOARD_INIT lets SPL common code call spl_board_init()
> during the SPL start up. On this particular system, spl_board_init()
> is used to reconfigure GIC clock parent to PLL2 500M, which is the
> configuration expected by the Li
On Fri, Jan 19, 2024 at 1:09 PM Marek Vasut wrote:
>
> The CONFIG_SPL_BOARD_INIT lets SPL common code call spl_board_init()
> during the SPL start up. On this particular system, spl_board_init()
> is used to reconfigure GIC clock parent to PLL2 500M, which is the
> configuration expected by the Li
On Fri, Jan 19, 2024 at 9:36 PM Marek Vasut wrote:
>
> Linux 6.6.y with KASLR enabled would print the following message on boot:
> "
> KASLR disabled due to lack of seed
> "
> Enable the 'kaslrseed' command so a random number seed can be pulled
> from CAAM and inserted into the /chosen node 'kaslr
the Armada3700 Secure Processor. This rng is onlt accessible
to the rWTM firmware. Currently the CZ.NIC Turris Mox firmware
exposes this.
For the Linux kernel a driver called turris-mox-rwtm exists that
makes use of this feature. This RNG driver for U-Boot tries to do the
same.
For efficiency I c
usable on all armada3700 devices with CZ.NIC firmware
compatible with devices with default firmware (does nothing)
based on Linux turris-mox-rwtm module
Signed-off-by: Max Resch
---
drivers/rng/Kconfig | 8 ++
drivers/rng/Makefile | 1 +
drivers/rng/turris_rwtm_rng.c | 14
On Sat, 23 Dec 2023 06:51:59 +, Shantur Rathore wrote:
> We need BOOTSTD_DEFAULT when BOOTSTD_FULL is selected.
>
>
Applied to u-boot/master, thanks!
--
Tom
On Sat, 20 Jan 2024 14:27:23 +0100
Max Resch wrote:
Hello Max,
please follow the conventions for commit titles and messages. Look for
example at
git log drivers/rng
The commit title should be something like
rng: Add Turris Mox rWTM RNG driver
> usable on all armada3700 devices with CZ.NIC f
Make the "phy-handle" property optional, which allows support
for a fixed-link phy configuration.
Thus if the "phy-handle" is present in a DT, then driver will work as
before. Otherwise, phyaddr initialization will not be necessary,
as it is not needed in case of a fixed-link config.
Signed-off-b
On Tue, Jan 09, 2024 at 01:14:55PM -0600, Nishanth Menon wrote:
> This is a wide cleanup to switch to setting fdtfile using env_set
> instead of scripted magic. 'fdtfile' is expected to be set by default.
> This allows the stdboot triggered efi loaders to find the correct OS
> device tree file eve
On Mon, Jan 15, 2024 at 01:42:51PM +0530, Siddharth Vadapalli wrote:
> Hello Tom,
>
> On 12/01/24 18:56, Tom Rini wrote:
> > On Fri, Jan 12, 2024 at 12:17:50PM +0530, Siddharth Vadapalli wrote:
> >
> >> From: Kishon Vijay Abraham I
> >>
> >> Call dram_init_banksize() from spl_board_init() otherw
On Mon, Jan 15, 2024 at 01:40:00PM +0200, Roger Quadros wrote:
>
>
> On 12/01/2024 15:21, Tom Rini wrote:
> > On Fri, Jan 12, 2024 at 07:14:50AM -0600, Nishanth Menon wrote:
> >> On 15:06-20240112, Roger Quadros wrote:
> >>>
> >>>
> >>> On 12/01/2024 15:02, Nishanth Menon wrote:
> On 14:49-2
T114 is not that different from T30 and all T30 drivers will work
on T114 as well with some adjustments.
Patches propose general improvements for existing Tegra DC and DSI
drivers as well Tegra 114 video support (experimentl).
Commits pass buildman for tegra.
---
Changes from v4:
- fixed typo i
Subtracting 1 from x and y fixes image shifting on rotated
panels.
Tested-by: Robert Eckelmann # ASUS Grouper E1565
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/tegra20/tegra-dc.c b/dri
Diverge DC driver setup to better fit each of supported generations
of Tegra SOC.
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Robert Eckelmann # ASUS TF101
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegr
Consolidate HD headers and place the result into video/tegra20
since it is used only by devices from this directory.
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Robert Eckelmann # ASUS TF101
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HTC One X
Tested-
Tegra SoC has 2 independent display controllers called DC_A and
DC_B, they are handled differently by internal video devices like
DSI and HDMI controllers so it is important for last to know
which display controller is used to properly set up registers.
To achieve this, a pipe field was added to pd
T30+ SOC have second PLLD - PLLD2 which can be actively used by
DC and act as main DISP1/2 clock parent.
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Robert Eckelmann # ASUS TF101
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatosl
Implement reset use to discard any changes which could have been
applied to DC before and can interfere with current configuration.
Tested-by: Agneli # Toshiba AC100 T20
Tested-by: Robert Eckelmann # ASUS TF101
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HT
Add powergate use on T114 to complete resetting of DC.
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dc.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 35abb6fe46..9a18e
Dedicated MIPI calibration driver is used on T114 and newer. Before
T114 MIPI calibration registers were part of VI and CSI.
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/Makefile | 2 +-
drivers/video/tegra20/tegra-mipi.c | 1
If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause
of this is not quite clear. This can be overcomed by further
halving the DISP1 clock if its parent is PLLD/D2 and the target
rate is > 400MHz.
Tested-by: Andreas Westman Dorcsak # ASUS Grouper E1565
Tested-by: Ion Agorria # HTC One
Existing Tegra DSI driver mostly fits T114 apart MIPI calibration
which on T114 has dedicated driver. To resolve this MIPI calibration
logic was split for pre-T114 and T114+ devices.
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Svyatoslav R
From: Jonas Schwöbel
Configuration for DC driver command mode is not required for
every panel. Removed.
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Jonas Schwöbel
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dsi.c |
Implement reset use to discard any changes which could have been
applied to DSI before and can interfere with current configuration.
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel
---
drivers/video/tegra20/tegra-dsi.c | 14
From: Jonas Schwöbel
According to Thierry Reding's commit in the linux kernel
976cebc35bed0456a42bf96073a26f251d23b264
"drm/tegra: dsi: Make FIFO depths host parameters"
correct depth of the video FIFO is 1920 *words* no *bytes*
Tested-by: Ion Agorria # HTC One X
Tested-by: Svyatoslav Ryhel
On Fri, 12 Jan 2024 14:49:46 +0200, Roger Quadros wrote:
> This series fixes USB operation on k3-j721e based boards.
>
> CI testing: https://github.com/u-boot/u-boot/pull/468
>
> cheers,
> -roger
>
> [...]
Applied to u-boot/master, thanks!
--
Tom
Add THRU0-3 and SIOPBI/SIOPBO pin groups/functions.
Signed-off-by: Ivan Mikhaylov
---
arch/arm/dts/ast2600.dtsi| 20
drivers/pinctrl/aspeed/pinctrl_ast2600.c | 30
2 files changed, 50 insertions(+)
diff --git a/arch/arm/dts/ast2600.dtsi
On Thu, 28 Dec 2023 13:29:15 +0800
Chuanhong Guo wrote:
Hi,
thanks for taking care and sending a patch!
> FriendlyElec NanoPi Duo2 is a tiny SBC with Allwinner H3 and
> Ampak AP6212 WiFi module. The device-tree for it is already
> available in u-boot source tree. Add a default config for it.
>
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