Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.
Signed-off-by: Chanho Park
---
drivers/clk/starfive/clk-jh7110.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/starfive/clk-jh7110.c
b/drivers/clk/starfive/clk-jh7110.c
index 31aaf3340f94..a8
Adds jh7110 trng device tree node.
Signed-off-by: Chanho Park
---
arch/riscv/dts/jh7110.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index ec237a46ffba..13c47f7caa36 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch
This patchset adds to support StarFive JH7110 TRNG driver. Due to lack
of readl_relaxed API, the first patch tries to import the
APIs(read/write_relaxed) from Linux kernel's implementation. The second
patch adds the missing security clocks which are required by the trng
IP.
This IP can support 128
Enables JH7110 RNG driver to visionfive2 board.
Signed-off-by: Chanho Park
---
configs/starfive_visionfive2_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index b21754feafce..b15e7d24db19 100644
---
This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h
to use read/write[b|w|l|q]_relaxed functions.
Signed-off-by: Chanho Park
---
arch/riscv/include/asm/io.h | 45 +
1 file changed, 45 insertions(+)
diff --git a/arch/riscv/include/asm/io.h b
Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.
Signed-off-by: Chanho Park
---
drivers/rng/Kconfig | 6 +
drivers/rng/Makefile | 1 +
dr
On 10/28/23 07:35, Simon Glass wrote:
Hi Michal,
On Wed, 6 Sept 2023 at 12:22, Michal Simek wrote:
Hi Simon,
út 25. 7. 2023 v 23:36 odesílatel Simon Glass napsal:
In moving from v0.8 to v0.9 the Firmware Handoff specification made some
changes, including:
- Use a packed format for
On Sun, Oct 29, 2023 at 09:45:32AM +0100, Heinrich Schuchardt wrote:
> If CSRs like seed are readable by S-mode, may not be determinable by
> S-mode. For safe driver probing allow to resume via a longjmp after an
> exception.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> new patch
>
On Sun, Oct 29, 2023 at 09:45:33AM +0100, Heinrich Schuchardt wrote:
> The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
> provides an interface to a physical entropy source.
>
> A RNG driver based on the seed CSR is provided. It depends on
> mseccfg.sseed being set in the SBI
On Wed, Oct 25, 2023 at 12:15:43AM +0200, Heinrich Schuchardt wrote:
> Use the most recent upstream release of OpenSBI for CI testing.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> .azure-pipelines.yml | 8
> .gitlab-ci.yml | 8
> 2 files changed, 8 insertions(+), 8 dele
On Sun, Oct 29, 2023 at 05:28:12PM +1300, Simon Glass wrote:
> Add support for the self-test continue command in the TPM v1.2 emulator,
> to match the functionality in the TPM v2 emulator.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/tpm/tpm_tis_sandbox.c | 1 +
> 1 file changed, 1 insertio
On Sun, 29 Oct 2023 23:37:22 +0100
Marek Vasut wrote:
> Add support for exposing the whole mmc device by setting the 'size'
> parameter to 0. This can be useful in case it is not clear what the
> total device size is up front. Update the documentation accordingly.
>
> Signed-off-by: Marek Vasut
This series adds support of AM62x LP SK. The AM62x LP SK board
is similar to AM62x SK but has some significant changes that
requires different set of device tree at each stage of bootloader.
Also refactors to have common nodes at k3-am62x-r5-sk-common.dtsi
and k3-am62x-sk-common-u-boot.dtsi for all
Add k3-am62x-r5-sk-common to include nodes common for R5
SPL from k3-am625-r5-sk for AM62x SoC based boards. Add
k3-am62x-sk-common-u-boot to move common nodes of A53 SPL
stage from k3-am625-sk-u-boot.
Replace 'bootph-pre-ram' from 'bootph-all' as it's not available
at u-boot proper before relocat
Add defconfig fragments for AM62x LP SK for for AM62x LP SK.
Signed-off-by: Nitin Yadav
---
board/ti/am62x/am62x_lpsk_a53.config | 5 +
board/ti/am62x/am62x_lpsk_r5.config | 5 +
2 files changed, 10 insertions(+)
create mode 100644 board/ti/am62x/am62x_lpsk_a53.config
create mode 1006
The AM62x LP SK board is similar to the AM62x SK board,
but has some significant changes that requires different
device tree.
The differences are mainly:
- AM62x SoC in the AMC package that meets AECQ100 automotive standard.
- LPDDR4 versus DDR4 on the AM62x SK.
- TPS65219 PMIC instead of discrete
Add link for AM62x LP SK in platform information. AM62x LP SK
has config fragments to build U-boot, Adding information to
update UBOOT_CFG_CORTEXR with lpsk fragments over am62x defconfig.
Signed-off-by: Nitin Yadav
---
doc/board/ti/am62x_sk.rst | 8
1 file changed, 8 insertions(+)
dif
Hi Tom
On Sun, 29 Oct 2023 at 16:33, Tom Rini wrote:
>
> On Sun, Oct 29, 2023 at 05:28:13PM +1300, Simon Glass wrote:
>
> > Some of the Python tests are a pain because they don't reset the TPM
> > state before each test. Driver model tests do this, so convert the
> > tests to C.
> >
> > This mean
Hi Simon,
Thanks for fixing this.
On Sun, 29 Oct 2023 at 06:28, Simon Glass wrote:
>
> Some of the Python tests are a pain because they don't reset the TPM
> state before each test. Driver model tests do this, so convert the
> tests to C.
>
> This means that these tests won't run on real hardwar
On Sun, 29 Oct 2023 at 06:28, Simon Glass wrote:
>
> These don't seem to be needed.
Please metnion something we can refer to in the future. e.g.
"A previous patch moves most of the sandbox tests to C code, those
arent needed anymore" etc
>
> Add a few notes about what to do next. Also mention pa
Thanks Simon,
Apart from a nit in patch#2 this looks good.
Pleas note that this doesn't apply on -master so please rebase
On Sun, 29 Oct 2023 at 06:28, Simon Glass wrote:
>
> This series is a starting point only. It tries to provide some direction
> for how the TPM tests should be run on real ha
RV1126 fails to boot on 2024.01-rc1.
Commit 9e64428 changed the behaviour of bootph-pre-ram, to limit
nodes to spl phase. This caused rv1126 boards to fail to boot
with the current dts.
This patch updates the pmu/grf nodes to bootph-all tags as they are
needed in all phases. This fixes the boot i
On Sun, Aug 20, 2023 at 10:03:18PM +, Jonas Karlman wrote:
> Nodes with bootph-pre-sram/ram props are bound in multiple phases:
> 1. At TPL (bootph-pre-sram) or SPL (bootph-pre-ram) phase
> 2. At U-Boot proper pre-relocation phase
> 3. At U-Boot proper normal phase
>
> However the binding and
On Sun, Oct 29, 2023 at 05:46:12AM +1300, Simon Glass wrote:
> Hi Masahiro,
>
> Sure, but that is a separate issue, isn't it? We already support
> various boot targets in arm64 but not one that includes the DTs, so
> far as I can see. The old arm 'uImage' target is pretty out-of-date
> now.
Does
Hey all,
Now that checkpatch.pl complains about adding common.h to new files, I
would like to ask custodians to try and fixup patches that had been
submitted already and use the header. In general, we can just drop the
file entirely. If we can't it's often a quick fix of which include file
was mis
On Mon, Oct 30, 2023 at 03:35:34PM +, Russell King (Oracle) wrote:
> On Sun, Oct 29, 2023 at 05:46:12AM +1300, Simon Glass wrote:
> > Hi Masahiro,
> >
> > Sure, but that is a separate issue, isn't it? We already support
> > various boot targets in arm64 but not one that includes the DTs, so
>
From: Jan Kiszka
We are not iterating CQSPI_REG_RETRY, we are waiting 'timeout' ms, since
day 1.
Signed-off-by: Jan Kiszka
---
We are unfortunately seeing that message right now, rarely but then
prominently...
drivers/spi/cadence_qspi_apb.c | 3 +--
1 file changed, 1 insertion(+), 2 deletio
The sysreset uclass unconditionally provides a definition of the
reset_cpu() function. So does the exynos soc code. Fix the build with
SYSRESET enabled by omitting the function from the soc code in that
case. The code still needs to be kept around for use in SPL.
This commit was inspired by commit
EEPROM detection logic in ti_i2c_eeprom_get() involves reading
the total size and the 1-byte size with an offset 1. The commit
9f393a2d7af8 ("board: ti: common: board_detect: Fix EEPROM read
quirk for 2-byte") that attempts to fix this uses a wrong pointer to
compare.
The value with one offset is
Buildman assumes that branch names do not have a slash in them, since
slash is used to delimit remotes, etc. This means that a branch called
'WIP/tryme' in remote dm ends up being 'tryme'.
Adjust the logic a little, to try to accommodate this.
For now, no tests are added for this behaviour.
Sign
On Mon, Oct 30, 2023 at 11:55:02AM -0500, Sam Protsenko wrote:
> The sysreset uclass unconditionally provides a definition of the
> reset_cpu() function. So does the exynos soc code. Fix the build with
> SYSRESET enabled by omitting the function from the soc code in that
> case. The code still nee
On Mon, Oct 30, 2023 at 10:22:30AM -0700, Simon Glass wrote:
> Buildman assumes that branch names do not have a slash in them, since
> slash is used to delimit remotes, etc. This means that a branch called
> 'WIP/tryme' in remote dm ends up being 'tryme'.
>
> Adjust the logic a little, to try to
During scanning for the next bootdev, if bootdev_next_prio() encounters
a device error (e.g. ENOSYS), let it continue scanning the next devices,
not stopping prematurely.
Background:
During scanning for bootflows, it's possible for bootstd to encounter a
faulty device controller. Also when the sa
On Sat, Oct 28, 2023 at 05:55:35PM +0200, Marek Vasut wrote:
> The following changes since commit fb428b61819444b9337075f49c72f326f5d12085:
>
> Merge branch '2023-10-24-assorted-general-fixes-and-updates' (2023-10-24
> 19:12:21 -0400)
>
> are available in the Git repository at:
>
> https:/
On Thu, Oct 19, 2023 at 11:04:35AM -0400, Tom Rini wrote:
> Make it clear that in the options for setting the console record buffer
> sizes that we are talking about buffers for that feature specifically
> and not the general console buffers.
>
> Signed-off-by: Tom Rini
Applied to u-boot/master
On Tue, Oct 24, 2023 at 09:26:38AM +0200, Heinrich Schuchardt wrote:
> Do not leak file descriptor if writing fails.
> Correct the error text if opening a file fails.
>
> Addresses-Coverity-ID: 467054 Resource leaks
> Fixes: 64fd30d367a1 ("tools: mkimage: Add StarFive SPL image support")
> Signed
On Fri, Oct 20, 2023 at 02:15:33PM +0100, Abdellatif El Khlifi wrote:
> address the CID 464361 Control flow issues [1]
>
> [1]: https://lore.kernel.org/all/20230821210927.GL3953269@bill-the-cat/
>
> Signed-off-by: Abdellatif El Khlifi
> Cc: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
On Sat, Oct 28, 2023 at 12:58:27PM -0400, Tom Rini wrote:
> Update U-Boot's version of scripts/get_maintainer.pl to sync it up with
> the latest changes to the Linux kernel's version of the same script.
>
> The last sync was with Linux kernel version v5.13-rc6. The commits to
> the kernel's get_m
On Thu, Oct 26, 2023 at 05:47:41AM +, Michel Alex wrote:
> Calculate the maximum length of the buffer when writing
> across the page boundary. If the buffer length (len)
> exceeds the page boundary (pagesize), split it. Use this
> length instead of comparing the length with the pagesize,
> bec
On Tue, Jul 25, 2023 at 09:50:40AM +0300, Dan Carpenter wrote:
> The > comparison needs to be changed to >= to prevent an out of bounds
> write on th next line.
>
> Signed-off-by: Dan Carpenter
> Reviewed-by: Simon Glass
While Simon had comments of a more general nature that would be good to
h
On Wed, Oct 25, 2023 at 09:25:37AM +0200, Michal Simek wrote:
> Similar change was done by commit b4c2c151b14b ("Kconfig: Remove all
> default n/no options") and again sync is required.
>
> default n/no doesn't need to be specified. It is default option anyway.
>
> Signed-off-by: Michal Simek
>
This driver is just a stub, but it's necessary to support the upcoming
reset driver changes.
Signed-off-by: Caleb Connolly
---
arch/arm/Kconfig | 1 +
arch/arm/mach-ipq40xx/Makefile | 1 -
drivers/clk/qcom/Kconfig
This series begins making some headway towards cleaning up Qualcomm
platform support in u-boot. The following is a rough overview of the
changes:
* Move the Qualcomm clock drivers out of mach-snapdragon and into clk/qcom
* Introduce per-platform clock driver configs to decouple Qualcomm platform
Clock drivers don't belong here, move them to the right place and
declutter mach-snapdragon a bit.
To de-couple these drivers from specific "target" platforms, add
additional config options to enable each clock driver gated behind a
common CLK_QCOM option and enable them by default for the respect
Many gate clocks can be enabled with a single register write, add support
for defining these simple gate clocks and add the ones found on SDM845.
While we're here, inline clk_init_uart() into msm_set_rate().
Signed-off-by: Caleb Connolly
---
.../mach-snapdragon/include/mach/sysmap-sdm845.h |
From: Konrad Dybcio
Qualcomm's clock controller blocks actually do much more than it
says on the tin.. They provide clocks, resets and power domains.
Currently, U-Boot requires one to spawn 2 separate devices for
controlling clocks and resets, both spanning the same register space.
Refactor the c
Currently, it isn't possible to build clock drivers for more than one
platform due to how the msm_enable() and msm_set_rate() callbacks are
implemented.
Extend qcom_clk_data to include function pointers for these and convert
all platforms to use them.
Previously, clock drivers relied on include/c
This property is needed on some platforms to ensure that only the
relevant bits are set in the M/N/D registers.
Signed-off-by: Caleb Connolly
Reviewed-by: Sumit Garg
---
drivers/clk/qcom/clock-apq8016.c | 4 ++--
drivers/clk/qcom/clock-apq8096.c | 4 ++--
drivers/clk/qcom/clock-qcom.c| 11
The RCG divider field takes a value of (2*h - 1) where h is the divisor.
This allows fractional dividers to be supported by calculating them at
compile time using a macro.
However, the clk_rcg_set_rate_mnd() function was also performing the
calculation. Clean this all up and consistently use the F
This series adds support for reading the otp on rv1126 and
then uses this to generate a persistant MAC address from cpuid.
Tim Lunn (2):
rockchip: otp: Add support for RV1126
rockchip: rv1126: Read cpuid from otp and set ethaddr
arch/arm/dts/rv1126-u-boot.dtsi | 12 ++
arch/arm/mach-rock
Extend the otp driver to read rv1126 otp. This driver code was
adapted from the Rockchip BSP stack.
Signed-off-by: Tim Lunn
---
drivers/misc/rockchip-otp.c | 76 +
1 file changed, 76 insertions(+)
diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockch
Provide configuration to read cpuid and generate a persistant
MAC address in ethaddr
Signed-off-by: Tim Lunn
---
arch/arm/dts/rv1126-u-boot.dtsi | 12
arch/arm/mach-rockchip/Kconfig | 2 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/
CONFIG_ARCH_SUNXI will not be enabled for RISC-V SoCs using this driver.
Use the symbol for the driver itself instead.
Signed-off-by: Samuel Holland
---
drivers/clk/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 26b
sunxi platforms put .bss in DRAM, so .bss is not available in SPL before
DRAM controller initialization. Therefore, this buffer must be placed in
the .data section.
Signed-off-by: Samuel Holland
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
On 7/10/23 22:00, David Hewitt wrote:
> This is required for correct booting of the PINE64 PineTab2. If
> PWREN is pulled high on this device, the SD card cannot be detected.
>
> This is required in other PINE64 devices (e.g. Quartz64 Model A) too.
>
> See commit ba33172a36f298641f51a5e6b855c3e89
On 7/16/23 03:34, Svyatoslav Ryhel wrote:
> Existing PALMAS PMIC driver is fully compatible with TI TPS65913
> PMIC found in many Tegra 4 devices, like Tegra Note 7 and ASUS
> TF701T. TPS65913 shares same structure of regulators like TPS659038
> so data can be reused.
>
> Tested-by: Svyatoslav Ryh
On 7/16/23 03:34, Svyatoslav Ryhel wrote:
> Currently device tree entries of regulators are completely
> ignored and regulators are probed only if they are called
> by the device which uses it. This results into two issues:
> regulators which must run under boot-on or always-on mode
> are ignored a
On 8/24/23 00:45, Oleksandr Suvorov wrote:
> mmc_bind() in mmc-uclass.c calls blk_create_devicef() which is
> defined in blk-uclass.c, so SPL_BLK is required by SPL_DM_MMC.
> Implicitly select SPL_BLK for SPL_DM_MMC.
>
> Signed-off-by: Oleksandr Suvorov
> Reviewed-by: Tom Rini
Reviewed-by: Jaeh
On 9/25/23 07:30, Sidharth Prabukumar wrote:
> The MP5416 PMIC's LDO set-value formula is incorrect. This patch fixes
> it by using the correct formula.
>
> Signed-off-by: Sidharth Prabukumar
> Cc: Jaehoon Chung
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
> include/power/mp
On 10/3/23 13:16, Kuan Lim Lee wrote:
> When selecting MMCSD_MODE_EMMCBOOT as boot_mode, emmc do not load U-boot
> proper image after switched hardware partition.
>
> Signed-off-by: Kuan Lim Lee
> Reviewed-by: Chee Hong Ang
> Reviewed-by: Wei Liang Lim
Reviewed-by: Jaehoon Chung
Best Regard
If the UART bus or baud clock has a gate, it must be enabled before the
UART can be used.
Reviewed-by: Stefan Roese
Signed-off-by: Samuel Holland
---
Changes in v3:
- Switch back to the original patch, now that the phycore-rk3288 build
is fixed by enabling LTO.
Changes in v2:
- Only enabl
31 жовтня 2023 р. 07:02:54 GMT+02:00, Jaehoon Chung
написав(-ла):
>On 7/16/23 03:34, Svyatoslav Ryhel wrote:
>> Existing PALMAS PMIC driver is fully compatible with TI TPS65913
>> PMIC found in many Tegra 4 devices, like Tegra Note 7 and ASUS
>> TF701T. TPS65913 shares same structure of regula
31 жовтня 2023 р. 07:03:17 GMT+02:00, Jaehoon Chung
написав(-ла):
>On 7/16/23 03:34, Svyatoslav Ryhel wrote:
>> Currently device tree entries of regulators are completely
>> ignored and regulators are probed only if they are called
>> by the device which uses it. This results into two issues:
Hi,
If will resend this patch according Simon's comment, I will check again.
Best Regards,
Jaehoon Chung
> -Original Message-
> From: Simon Glass
> Sent: Wednesday, July 19, 2023 10:08 AM
> To: Svyatoslav Ryhel
> Cc: Jaehoon Chung ; Patrick Delaunay
> ; u-
> b...@lists.denx.de
> Subje
31 жовтня 2023 р. 07:11:02 GMT+02:00, Jaehoon Chung
написав(-ла):
>Hi,
>
>If will resend this patch according Simon's comment, I will check again.
>
>Best Regards,
>Jaehoon Chung
>
It will not be updated since it was split into 2 different bigger patchsets one
of which was dropped as well. Yo
This series makes the necessary changes so 32-bit sunxi SoCs can load
additional device trees or firmware from SPL along with U-Boot proper.
Crust (SCP firmware) has support for A33 and H3, and H3 also needs to
load an eGon blob to support CPU 0 hotplug (a silicon bug workaround).
FIT unlocks more
Starting with H6, Allwinner removed the artificial 32 KiB SPL size limit
from the boot ROM. Now SPL size is only limited by the available SRAM.
This limit ranges from 152 KiB on H6 to a whopping 2052 KiB on R329. To
take advantage of this additional space, we must increase SPL_MAX_SIZE.
Since we do
This is easier to read than the #ifdef staircase, provides better
visibility into the memory map (alongside the other Kconfig
definitions), and allows these addresses to be reused from code.
Reviewed-by: Simon Glass
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- New
Some 32-bit SoCs can use SCP firmware to implement additional PSCI
functionality, such as system suspend. In order to load this firmware
from SPL, we need to generate and use a FIT instead of a legacy image.
Adjust the binman FIT definition so it does not rely on TF-A BL31, as
this is not used on
Now that 32-bit SoCs can load U-Boot proper (and possibly other
firmware) from a FIT, use this method by default. SPL_FIT_IMAGE_TINY is
required to stay within the 24 or 32 KiB SPL size limit on early SoCs;
for consistency, enable it everywhere.
Signed-off-by: Samuel Holland
---
(no changes sinc
commit 95168d77d391 ("sunxi: add Allwinner R528/T113 SoC support") added
the new entry out of order.
Signed-off-by: Samuel Holland
---
drivers/mmc/sunxi_mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 4d6351bf275.
The MMC controller driver is (and ought to be) the only user of these
register definitions. Put them in a header next to the driver to remove
the dependency on a specific ARM platform's headers.
Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
the register definitions were
DM_GPIO is always enable in U-Boot proper for ARCH_SUNXI, and this
driver is never enabled in SPL, so the condition is always true.
Signed-off-by: Samuel Holland
---
drivers/net/sun8i_emac.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/su
Clean things up for the next time somebody adds a target.
Signed-off-by: Samuel Holland
---
arch/riscv/Kconfig | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8fc81fb284c..6d0d812ddb5 100644
--- a/arch/riscv/Kc
This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."
Reported-by: Madushan Nishantha
Signed-of
Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().
Signed-off-by: Samuel Holland
---
arch/riscv/lib/cache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
Hi Marek,
On 10/10/23 21:47, Marek Vasut wrote:
> Add extension to the 'mmc' command to read out the card registers.
> Currently, only the eMMC OCR/CID/CSD/EXTCSD/RCA/DSR register are
> supported. A register value can either be displayed or read into
> an environment variable.
>
> Signed-off-by:
On 10/11/23 20:00, Bin Meng wrote:
> dm_pci_map_bar() return a value of (void *) already, hence no need
> to cast it again before assigning to host->ioaddr.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Simon Glass
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
>
> drivers/mmc/p
On 10/19/23 00:50, Andre Przywara wrote:
> The X-Powers AXP313a is a small PMIC with just three buck converters and
> three LDOs, one of which is actually fixed (so not modelled here).
>
> Add the compatible string and the respective regulator ranges to allow
> drivers to adjust voltages.
>
> Sig
drivers/rng/riscv_zkr_rng.c:10:10: fatal error: interrupt.h: No such
file or directory
10 | #include
| ^
compilation terminated.
Where is this interrupt.h?
Regards,
Xiang W
Heinrich Schuchardt 于2023年10月29日周日 16:46写道：
>
> The Zkr ISA extension (ratified Nov 2021) introduced the seed
Hi,
> -Original Message-
> From: U-Boot On Behalf Of Jaehoon Chung
> Sent: Tuesday, October 31, 2023 3:08 PM
> To: Marek Vasut ; u-boot@lists.denx.de
> Cc: Abdellatif El Khlifi ; Heinrich Schuchardt
> ;
> Ilias Apalodimas ; Ramon Fried
> ; Roger Knecht
> ; Sean Edmond ; Simon Glass
> ;
> -Original Message-
> From: Samuel Holland
> Sent: Tuesday, October 31, 2023 2:23 PM
> To: u-boot@lists.denx.de; Jagan Teki ; Andre
> Przywara
>
> Cc: Samuel Holland ; Jaehoon Chung
> ; Peng Fan
>
> Subject: [PATCH 1/2] sunxi: mmc: Sort compatible strings numerically
>
> commit 95
> -Original Message-
> From: Samuel Holland
> Sent: Tuesday, October 31, 2023 2:23 PM
> To: u-boot@lists.denx.de; Jagan Teki ; Andre
> Przywara
>
> Cc: Samuel Holland ; Jaehoon Chung
> ; Peng Fan
>
> Subject: [PATCH 2/2] sunxi: mmc: Move header to the driver directory
>
> The MMC c
merle w schrieb am Di., 31. Okt. 2023, 08:16:
> drivers/rng/riscv_zkr_rng.c:10:10: fatal error: interrupt.h: No such
> file or directory
> 10 | #include
> | ^
> compilation terminated.
>
> Where is this interrupt.h?
>
Please, see patch 1/2.
Best regards
Heinrich
> Regards,
> Xi
This series converts sunxi boards from controlling VBUS suppllies using
GPIO name strings in Kconfig to using regulator devices probed via the
devicetree. ARCH_SUNXI already implies DM_REGULATOR_FIXED, so the only
new driver needed is for the AXP PMIC drivevbus regulator. This is part
2 of 3 for re
AXP PMICs have a pin which can either report the USB VBUS state, or
driving a regulator that supplies USB VBUS. Add a regulator driver for
controlling this pin. The selection between input and output is done via
the x-powers,drive-vbus-en pin on the PMIC (parent) node.
Signed-off-by: Samuel Hollan
On many boards, the USB ports are powered by the PMIC's "drivevbus"
regulator. In preparation for switching the USB PHY driver to use the
regulator uclass instead of a virtual GPIO pin, ensure these boards
have AXP PMIC regulator support enabled.
Signed-off-by: Samuel Holland
---
configs/A33-OL
The device tree binding for the PHY provides VBUS supplies as regulator
references. Now that all boards have the appropriate regulator uclass
drivers enabled, the PHY driver can switch to using them. This replaces
direct GPIO usage, which in some cases needed a special DM-incompatible
"virtual" GPI
Now that the USB PHY driver uses the device tree to get VBUS supply
regulators, these Kconfig symbols are unused. Remove them.
Signed-off-by: Samuel Holland
---
arch/arm/mach-sunxi/Kconfig | 29
configs/A10s-OLinuXino-M_defconfig | 1 -
configs/A
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove
it, along with the rest of the support for AXP virtual GPIOs.
Signed-off-by: Samuel Holland
---
drivers/gpio/axp_gpio.c | 75 +++
Hi,
> -Original Message-
> From: Andre Przywara
> Sent: Sunday, October 22, 2023 6:19 AM
> To: Jernej Škrabec
> Cc: Jagan Teki ; Jaehoon Chung
> ; Samuel Holland
> ; SASANO Takayoshi ; Mikhail
> Kalashnikov ;
> Piotr Oniszczuk ; u-boot@lists.denx.de;
> linux-su...@lists.linux.dev
> Su
> -Original Message-
> From: Svyatoslav Ryhel
> Sent: Friday, October 27, 2023 5:26 PM
> To: Tom Rini ; Jaehoon Chung ;
> Simon Glass
> ; Svyatoslav Ryhel
> Cc: u-boot@lists.denx.de
> Subject: [PATCH v9 1/8] power: pmic: palmas: support TI TPS65913 PMIC
>
> Existing PALMAS PMIC drive
Hi Xiang,
On Tue, Oct 31, 2023 at 02:16:22PM +0800, merle w wrote:
> drivers/rng/riscv_zkr_rng.c:10:10: fatal error: interrupt.h: No such
> file or directory
> 10 | #include
> | ^
> compilation terminated.
>
> Where is this interrupt.h?
I think this file is created by the first patch
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