Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"),
the maximum number of variable range MTRRs was increased from 8 to 10,
which caused a #GP exception during VESA video driver probe.
On the BayTrail platform there are only 8 variable range MTRRs. In
mtrr_commit() it still uses M
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> Sent: Thursday, November 05, 2020 7:31 PM
> To: u-boot@lists.denx.de
> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick
> Jian-Zhi Chen(陳建
This series will add support for MediaTek MT7620 SoC with two reference boards
and related drivers.
The MediaTek MT7620 is a 2x2 802.11n WiSoC integrating a MIPS 24KEc processor
running at a maximum frequency of 620MHz. This chip can be found in many
wireless routers.
This series add all basic dr
Previous the dts files for gardena-smart-gateway-mt7688 and
linkit-smart-7688 are set to be built when mtmips is selected.
This can lead to a compilation error if another soc is added to this arch
with different dtsi files.
So it's better to build the dtb only if their board is selected.
Reviewe
Currently only mt7628 needs the sysreset driver, do not select it for
mt7620.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: new
---
arch/mips/Kconfig | 1 -
arch/mips/mach-mtmips/Kconfig | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/Kconfi
This patch is a preparation for add a new soc fot mtmips.
Move all mt7628 related Kconfig (boards and UART selection) into mt7628
subdirectory and make sure the top directory of mtmips contains only
selection for SoCs.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v3 changes: none
v2
This patch adds support for mtmips SoCs to initialize the SDRAM.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
arch/mips/mach-mtmips/ddr_init.c | 59
arch/mips/mach-mtmips/include/mach/ddr.h | 4 ++
2 files changed, 63 insertions(+)
diff -
The sysreset driver has a config CONFIG_SPL_SYSRESET for the spl stage.
Change CONFIG_SYSRESET to CONFIG_IS_ENABLED(SYSRESET) will give spl a
chance to use _machine_restart instead of the sysreset driver.
Reviewed-by: Simon Glass
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: new
---
CONFIG_SYS_SDRAM_BASE points to cached memory, i.e. KSEG0, which is not
suitable for detecting memory size.
Replace CONFIG_SYS_SDRAM_BASE with KSEG1, and make dram_init() always do
memory size detection in any stage.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 ch
This patch adds support for MediaTek MT7620 SoC.
All files are dedicated for u-boot.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: remove use of common.h
---
arch/mips/dts/mt7620-u-boot.dtsi | 14 +
arch/mips/dts/mt7620.dtsi | 296 ++
Since mt7620 is added into Kconfig, the CONFIG_SOC_MT7628=y which is
omitted by default must be added back, otherwise make xxx_defconfig for
these boards will be configured for mt7620 platform.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
configs
The mt7620_rfb board supports integrated 10/100M PHYs plus two external
giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB.
The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a
16MB SPI-NOR flash.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes:
This patch adds uart support for MediaTek MT7620 and earlier SoCs.
The UART used by MT7620 is incompatible with the ns16550a driver.
All registers of this UART have different addresses. A special 16-bit
register for Divisor Latch is used to set the baudrate instead of the
original two 8-bit regist
This patch adds pinctrl support for MediaTek MT7620 SoC.
The MT7620 SoC supports only pinmux.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
drivers/pinctrl/mtmips/Kconfig | 9 ++
drivers/pinctrl/mtmips/Makefile | 1 +
drivers/pinctrl/mtmips/pinctrl-mt76
This patch adds reset controller bits definition header file for MediaTek
MT7620 SoC
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
include/dt-bindings/reset/mt7620-reset.h | 35
1 file changed, 35 insertions(+)
create mode 100644 include/dt-binding
This patch adds GPIO controller driver for MediaTek MT7620 SoC
Reviewed-by: Simon Glass
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
drivers/gpio/Kconfig | 8 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/mt7620_gpio.c | 146 +
This patch adds spi controller support for MediaTek MT7620 SoC.
The SPI controller supports two chip selects. These two chip selects are
implemented as two separate register groups, but they share the same bus
(DI/DO/CLK), only CS pins are dedicated for each register group.
Appearently these two r
This patch adds watchdog support for the Mediatek MT7620 SoC
Reviewed-by: Jagan Teki
Signed-off-by: Weijie Gao
---
v3 changes: add detail comments for mt7620_wdt_expire_now()
v2 changes: add expire_now
---
drivers/watchdog/Kconfig | 7 ++
drivers/watchdog/Makefile | 1 +
drivers/wa
This patch adds a clock driver for MediaTek MT7620 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
drivers/clk/mtmips/Makefile| 1 +
drivers/cl
This patch adds USB PHY driver for MediaTek MT7620 SoC
Signed-off-by: Weijie Gao
---
v3 changes: remove duplicated dev field in mt7620_usb_phy
v2 changes: none
---
drivers/phy/Kconfig | 7 +++
drivers/phy/Makefile | 1 +
drivers/phy/mt7620-usb-phy.c | 110 +++
The driver is missing pad control settings (pad delay and pad conf) for
the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will
encounter CRC error on data transfers.
This patch adds default pad control settings for mt7620_compat.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 ch
This patch adds ethernet driver for MediaTek MT7620 SoC.
The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in
7-port switch and two xMII interfaces (can be MII/RMII/RGMII).
The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 can be
configured to connect to either t
It turns out that the sclk cycles used by mt7620/mt7628 is the same as
other chips (20 bits, 1048576), not 65536.
This patch removes sclk_cycle_shift from dev_comp, and uses a macro with
a value 20 instead.
Signed-off-by: Weijie Gao
---
v3 changes: new
---
drivers/mmc/mtk-sd.c | 13
Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can
be probed before relocation even if u-boot,dm-pre-reloc is not present
in the dts.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: new
---
drivers/reset/reset-mtmips.c | 1 +
1 file changed, 1 insertion(+)
diff
Update maintainer for MediaTek MIPS platform
Acked-by: Stefan Roese
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
MAINTAINERS | 23 +++
1 file changed, 23 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 874cf2c0e5.
Currently this driver does not set the value of plat->cfg.f_max, which
results in that MMC framework will always run at the lowest frequency.
This patch sets plat->cfg.f_max to the maximum allowed frequency, which is
half of the source clock frequency.
Signed-off-by: Weijie Gao
---
v3 changes: n
Hi Rick,
>-Original Message-
>From: Rick Chen
>Sent: 09 November 2020 13:44
>To: Pragnesh Patel
>Cc: U-Boot Mailing List ; Atish Patra
>; Bin Meng ; Paul Walmsley (
>Sifive) ; Anup Patel ; Sagar
>Kadam ; Simon Glass ; Sean
>Anderson ; palmerdabb...@google.com; rick
>; Alan Kao
>Subject:
On 09.11.20 09:24, Weijie Gao wrote:
Currently only mt7628 needs the sysreset driver, do not select it for
mt7620.
Signed-off-by: Weijie Gao
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
v3 changes: none
v2 changes: new
---
arch/mips/Kconfig | 1 -
arch/mips/mach-mtmips/Kcon
On 09.11.20 09:24, Weijie Gao wrote:
The sysreset driver has a config CONFIG_SPL_SYSRESET for the spl stage.
Change CONFIG_SYSRESET to CONFIG_IS_ENABLED(SYSRESET) will give spl a
chance to use _machine_restart instead of the sysreset driver.
Reviewed-by: Simon Glass
Signed-off-by: Weijie Gao
On 09.11.20 09:24, Weijie Gao wrote:
This patch adds support for mtmips SoCs to initialize the SDRAM.
Signed-off-by: Weijie Gao
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
v3 changes: none
v2 changes: none
---
arch/mips/mach-mtmips/ddr_init.c | 59
arc
On 11/6/20 7:01 PM, Neil Armstrong wrote:
> On 06/11/2020 10:59, Jaehoon Chung wrote:
>> Hi,
>>
>> On 11/6/20 6:28 PM, Neil Armstrong wrote:
>>> Hi,
>>>
>>> On 06/11/2020 03:10, Jaehoon Chung wrote:
Hi,
I have checked U-boot on Odroid-C4 with v2020.10.
I found a problem about re
On 09.11.20 09:24, Weijie Gao wrote:
This patch adds support for MediaTek MT7620 SoC.
All files are dedicated for u-boot.
Signed-off-by: Weijie Gao
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
v3 changes: none
v2 changes: remove use of common.h
---
arch/mips/dts/mt7620-u-boot.dtsi
On 09.11.20 09:24, Weijie Gao wrote:
The mt7620_rfb board supports integrated 10/100M PHYs plus two external
giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB.
The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a
16MB SPI-NOR flash.
Signed-off-by: Weijie
On 09.11.20 09:25, Weijie Gao wrote:
This patch adds uart support for MediaTek MT7620 and earlier SoCs.
The UART used by MT7620 is incompatible with the ns16550a driver.
All registers of this UART have different addresses. A special 16-bit
register for Divisor Latch is used to set the baudrate i
On 09.11.20 09:25, Weijie Gao wrote:
This patch adds a clock driver for MediaTek MT7620 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
v3 changes:
On 09.11.20 09:25, Weijie Gao wrote:
This patch adds reset controller bits definition header file for MediaTek
MT7620 SoC
Signed-off-by: Weijie Gao
Just curious: Where are you including this file? I couldn't find it
in a quick search through the following patches. Perhaps its also
a good idea
On 09.11.20 09:26, Weijie Gao wrote:
This patch adds pinctrl support for MediaTek MT7620 SoC.
The MT7620 SoC supports only pinmux.
Signed-off-by: Weijie Gao
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
v3 changes: none
v2 changes: none
---
drivers/pinctrl/mtmips/Kconfig | 9 +
On 09.11.20 09:26, Weijie Gao wrote:
This patch adds watchdog support for the Mediatek MT7620 SoC
Reviewed-by: Jagan Teki
Signed-off-by: Weijie Gao
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
v3 changes: add detail comments for mt7620_wdt_expire_now()
v2 changes: add expire_now
---
dr
On 09.11.20 09:27, Weijie Gao wrote:
This patch adds GPIO controller driver for MediaTek MT7620 SoC
Reviewed-by: Simon Glass
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
drivers/gpio/Kconfig | 8 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/mt7620_gpio
On 09.11.20 09:27, Weijie Gao wrote:
This patch adds spi controller support for MediaTek MT7620 SoC.
The SPI controller supports two chip selects. These two chip selects are
implemented as two separate register groups, but they share the same bus
(DI/DO/CLK), only CS pins are dedicated for each
On 09.11.20 09:27, Weijie Gao wrote:
This patch adds USB PHY driver for MediaTek MT7620 SoC
Signed-off-by: Weijie Gao
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
v3 changes: remove duplicated dev field in mt7620_usb_phy
v2 changes: none
---
drivers/phy/Kconfig | 7 +++
driv
On Mon, 2020-11-09 at 09:51 +0100, Stefan Roese wrote:
> On 09.11.20 09:25, Weijie Gao wrote:
> > This patch adds reset controller bits definition header file for MediaTek
> > MT7620 SoC
> >
> > Signed-off-by: Weijie Gao
>
> Just curious: Where are you including this file? I couldn't find it
> i
On 09.11.20 09:27, Weijie Gao wrote:
This patch adds ethernet driver for MediaTek MT7620 SoC.
The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in
7-port switch and two xMII interfaces (can be MII/RMII/RGMII).
The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 c
On 09.11.20 09:28, Weijie Gao wrote:
It turns out that the sclk cycles used by mt7620/mt7628 is the same as
other chips (20 bits, 1048576), not 65536.
This patch removes sclk_cycle_shift from dev_comp, and uses a macro with
a value 20 instead.
Signed-off-by: Weijie Gao
Reviewed-by: Stefan Ro
On 09.11.20 09:28, Weijie Gao wrote:
The driver is missing pad control settings (pad delay and pad conf) for
the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will
encounter CRC error on data transfers.
This patch adds default pad control settings for mt7620_compat.
Signed-off-by:
On 09.11.20 09:28, Weijie Gao wrote:
Currently this driver does not set the value of plat->cfg.f_max, which
results in that MMC framework will always run at the lowest frequency.
This patch sets plat->cfg.f_max to the maximum allowed frequency, which is
half of the source clock frequency.
Signe
On 09.11.20 09:28, Weijie Gao wrote:
Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can
be probed before relocation even if u-boot,dm-pre-reloc is not present
in the dts.
Signed-off-by: Weijie Gao
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
v3 changes: none
v2 chang
On 09.11.20 09:57, Weijie Gao wrote:
On Mon, 2020-11-09 at 09:51 +0100, Stefan Roese wrote:
On 09.11.20 09:25, Weijie Gao wrote:
This patch adds reset controller bits definition header file for MediaTek
MT7620 SoC
Signed-off-by: Weijie Gao
Just curious: Where are you including this file? I
On Mon, 2020-11-09 at 10:00 +0100, Stefan Roese wrote:
> On 09.11.20 09:28, Weijie Gao wrote:
> > The driver is missing pad control settings (pad delay and pad conf) for
> > the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will
> > encounter CRC error on data transfers.
> >
> > This
On 09.11.20 00:58, Paulo Alcantara wrote:
> The UEFI specification does not restrict on the number and location of
> ESPs in a system. They are discovered as required by looking at the
> partition type, but firmware implementations are allowed to support
> ESPs which do not contain a valid partiti
Add DFU_SKIP layout ccocept.
If layout is "skip", it will be skipped after nothing to do.
It's useful to support multiple board with one tar file.
Signed-off-by: Jaehoon Chung
Reviewed-by: Minkyu Kang
---
V2: Fix typo and Minkyu's reviewed-tag
---
doc/README.dfu| 10 +-
drivers/
Oops, Discard this.. Sorry.
On 11/9/20 8:51 PM, Jaehoon Chung wrote:
> Add DFU_SKIP layout ccocept.
> If layout is "skip", it will be skipped after nothing to do.
> It's useful to support multiple board with one tar file.
>
> Signed-off-by: Jaehoon Chung
> Reviewed-by: Minkyu Kang
> ---
> V2: F
Add DFU_SKIP layout concept.
If layout is "skip", it will be skipped after nothing to do.
It's useful to support multiple board with one tar file.
Signed-off-by: Jaehoon Chung
Reviewed-by: Minkyu Kang
---
V2: Fix typo and Minkyu's reviewed-tag
---
doc/README.dfu| 10 +-
drivers/
On 11/9/20 8:02 PM, Eugen Hristev wrote:
> If the clock driver does not offer a clk_enable ops, then the system will
> return -ENOSYS.
> The clk_enable works with CCF (common clock framework).
> Some clocks in some cases (like the generic clock for some products: sama5d2)
> do not have the clk_enab
On Thu, Nov 05, 2020 at 10:22:56AM -0700, Simon Glass wrote:
> Hi Tom,
>
> The following changes since commit 35b7ca768f7d826b77d5d3d6ccd6b1b8ed21f186:
>
> arch: Move NEEDS_MANUAL_RELOC symbol to Kconfig (2020-11-04 10:13:44
> -0500)
>
> are available in the Git repository at:
>
> git://gi
Heinrich Schuchardt writes:
> On 09.11.20 00:58, Paulo Alcantara wrote:
>> The UEFI specification does not restrict on the number and location of
>> ESPs in a system. They are discovered as required by looking at the
>> partition type, but firmware implementations are allowed to support
>> ESPs
Update From Linux commits
- 240051cb833b ("soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs")
- 1d7c541b8a5b ("soc: amlogic: meson-gx-socinfo: Add S905X3 ID for VIM3L")
- fdfc6997bd08 ("soc: amlogic: meson-gx-socinfo: Fix S905D3 ID for VIM3L")
- d16d0481e6ba ("soc: amlogic: meson-gx-socinfo: Fi
Hi,
On 09/11/2020 04:12, Jaehoon Chung wrote:
> Core clock phase value is changed from 180' to 270'.
> It's more stable than before.
> - Odroidn-N2/C4 : Working fine with 52MHz
> - VIM3 : Working fine with 52MHz
>
> Before this patch, Odroid-C4 doesn't work fine with 52MHz.
>
> Signed-off-by: Ja
On 09/11/2020 09:37, Jaehoon Chung wrote:
> On 11/6/20 7:01 PM, Neil Armstrong wrote:
>> On 06/11/2020 10:59, Jaehoon Chung wrote:
>>> Hi,
>>>
>>> On 11/6/20 6:28 PM, Neil Armstrong wrote:
Hi,
On 06/11/2020 03:10, Jaehoon Chung wrote:
> Hi,
>
> I have checked U-boot on Od
This somehow ended up as an empty file. Fix it.
Signed-off-by: Simon Glass
---
.../max98357-render-2ch-48khz-24b.dat | Bin 0 -> 116 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
b/board/google/ch
> From: Paulo Alcantara
> Date: Mon, 09 Nov 2020 10:24:08 -0300
>
> Heinrich Schuchardt writes:
>
> > On 09.11.20 00:58, Paulo Alcantara wrote:
> >> The UEFI specification does not restrict on the number and location of
> >> ESPs in a system. They are discovered as required by looking at the
>
On 09.11.20 14:24, Paulo Alcantara wrote:
> Heinrich Schuchardt writes:
>
>> On 09.11.20 00:58, Paulo Alcantara wrote:
>>> The UEFI specification does not restrict on the number and location of
>>> ESPs in a system. They are discovered as required by looking at the
>>> partition type, but firmwar
> From: Neil Armstrong
> Date: Mon, 9 Nov 2020 14:37:09 +0100
>
> Hi,
>
> On 09/11/2020 04:12, Jaehoon Chung wrote:
> > Core clock phase value is changed from 180' to 270'.
> > It's more stable than before.
> > - Odroidn-N2/C4 : Working fine with 52MHz
> > - VIM3 : Working fine with 52MHz
> >
>
The accepted binding uses multiple nodes, one for each table type. Update
coral accordingly.
Signed-off-by: Simon Glass
---
arch/x86/dts/chromebook_coral.dts | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/arch/x86/dts/chromebook_coral.dts
b/arc
At present if CONFIG_RESET is not enabled, this code shows a warning:
designware_i2c_ofdata_to_platdata() i2c_designware_pci i2c2@16,0:
Can't get reset: -524
Avoid this by checking if reset is supported, first.
Fixes: 622597dee4f ("i2c: designware: add reset ctrl to driver")
Signed-off
Make use of the new bootargs substitution mechanism and zboot command
syntax.
Signed-off-by: Simon Glass
---
include/configs/chromebook_coral.h | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/include/configs/chromebook_coral.h
b/include/configs/chromebook_coral.
With the updated changes to bootargs substitution[1], the zboot command
needs to be updated to get its command line from an environment variable
instead of a memory address. This is because the command-line string must
be updated to convert %U to ${uuid}, etc.
In any case it is more flexible to us
Erasing the flash can take over a second on some devices and the EC is
not responsive during this time. Update the timeout to 5 seconds to cope
with this.
Signed-off-by: Simon Glass
---
drivers/misc/cros_ec_lpc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mi
The EC now requires that the offset field be set correctly when checking
on hash status. Update the code to handle this. Use the same message
struct in both functions to reduce stack space.
Signed-off-by: Simon Glass
---
drivers/misc/cros_ec.c | 16 ++--
1 file changed, 10 insertion
On Mon, Nov 09, 2020 at 07:31:08PM +0530, Amit Singh Tomar wrote:
> after commit 4ab3817ff16a ("clk: fixed-rate: Enable DM_FLAG_PRE_RELOC flag")
> Cubieboard7 (based on actions S700 SoC) fails to boot.
>
> It is due to the fact that the default value of CONFIG_SYS_MALLOC_F_LEN
> (0x400)
> would n
On 09/11/2020 15:10, Mark Kettenis wrote:
>> From: Neil Armstrong
>> Date: Mon, 9 Nov 2020 14:37:09 +0100
>>
>> Hi,
>>
>> On 09/11/2020 04:12, Jaehoon Chung wrote:
>>> Core clock phase value is changed from 180' to 270'.
>>> It's more stable than before.
>>> - Odroidn-N2/C4 : Working fine with 52M
Mark Kettenis writes:
> The OpenBSD installation media for armv7 and arm64 use a FAT partition
> of type 0x0c because the Raspberry Pi firmware doesn't support 0xef.
> This allows us to have a single FAT partition with the Raspberry Pi
> firmware, U-Boot and /EFI/BOOT/BOOT{ARCH}.EFI.
Yeah, it is
On 09.11.20 14:51, Mark Kettenis wrote:
>> From: Paulo Alcantara
>> Date: Mon, 09 Nov 2020 10:24:08 -0300
>>
>> Heinrich Schuchardt writes:
>>
>>> On 09.11.20 00:58, Paulo Alcantara wrote:
The UEFI specification does not restrict on the number and location of
ESPs in a system. They are
At present if CROSS_COMPILE contains a tilde, such as
~/.buildman-toolchains/gcc-7.3.0-nolibc/i386-linux/bin/i386-linux-gcc
then binman gives a confusing error:
binman: Error 255 running '~/..buildman-toolchains/gcc-7.3.0- ...
Fix this by expanding it out before running the tool.
Signed-off-b
There is no need for GD to be used and priv variable is unused.
Signed-off-by: Michal Simek
---
drivers/tpm/tpm2_tis_spi.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
index 9a8145e6ba1f..0045bedf0c61 100644
--- a/drivers/tpm/tpm2
On 09.11.20 15:35, Paulo Alcantara wrote:
> Mark Kettenis writes:
>
>> The OpenBSD installation media for armv7 and arm64 use a FAT partition
>> of type 0x0c because the Raspberry Pi firmware doesn't support 0xef.
>> This allows us to have a single FAT partition with the Raspberry Pi
>> firmware,
after commit 4ab3817ff16a ("clk: fixed-rate: Enable DM_FLAG_PRE_RELOC flag")
Cubieboard7 (based on actions S700 SoC) fails to boot.
It is due to the fact that the default value of CONFIG_SYS_MALLOC_F_LEN (0x400)
would not provide enough memory for clock device to probe (before relocation)
well.
T
If the clock driver does not offer a clk_enable ops, then the system will
return -ENOSYS.
The clk_enable works with CCF (common clock framework).
Some clocks in some cases (like the generic clock for some products: sama5d2)
do not have the clk_enable primitive, and in this case probing of the drive
Hi Bin,
On Mon, 9 Nov 2020 at 01:05, Bin Meng wrote:
>
> Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"),
> the maximum number of variable range MTRRs was increased from 8 to 10,
> which caused a #GP exception during VESA video driver probe.
>
> On the BayTrail platform there
> From: Heinrich Schuchardt
> Date: Mon, 9 Nov 2020 15:36:33 +0100
>
> On 09.11.20 14:51, Mark Kettenis wrote:
> >> From: Paulo Alcantara
> >> Date: Mon, 09 Nov 2020 10:24:08 -0300
> >>
> >> Heinrich Schuchardt writes:
> >>
> >>> On 09.11.20 00:58, Paulo Alcantara wrote:
> The UEFI specifi
The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06
11:27:14 -0500)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
tags/efi-2021-01-rc2-2
for you to
Hi Neil,
On Mon, 9 Nov 2020 at 19:56, Neil Armstrong wrote:
>
> On 09/11/2020 15:10, Mark Kettenis wrote:
> >> From: Neil Armstrong
> >> Date: Mon, 9 Nov 2020 14:37:09 +0100
> >>
> >> Hi,
> >>
> >> On 09/11/2020 04:12, Jaehoon Chung wrote:
> >>> Core clock phase value is changed from 180' to 270
On 11/9/20 7:54 PM, Heinrich Schuchardt wrote:
> The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
>
> Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06
> 11:27:14 -0500)
>
> are available in the Git repository at:
>
> https://gitlab.denx.de/u-boot/
On Mon, Nov 09, 2020 at 08:15:43PM +0100, Heinrich Schuchardt wrote:
> On 11/9/20 7:54 PM, Heinrich Schuchardt wrote:
> > The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
> >
> > Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06
> > 11:27:14 -0500)
On 10/30/20 6:25 PM, Alper Nebi Yasak wrote:
> The cros_ec_keyb driver currently uses EC_CMD_MKBP_STATE to scan the
> keyboard, but this host command was superseded by EC_CMD_GET_NEXT_EVENT
> and unavailable on more recent devices (including gru-kevin), as it was
> removed in cros-ec commit 87a0719
Align the pin setup for sdhci0 with linux kernel.
This means to have slew rate enable and high drive strength.
Signed-off-by: Eugen Hristev
---
arch/arm/dts/sam9x60.dtsi | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/d
Hi Heinrich,
On Mon, 9 Nov 2020 at 12:34, Heinrich Schuchardt wrote:
>
> On 10/30/20 6:25 PM, Alper Nebi Yasak wrote:
> > The cros_ec_keyb driver currently uses EC_CMD_MKBP_STATE to scan the
> > keyboard, but this host command was superseded by EC_CMD_GET_NEXT_EVENT
> > and unavailable on more re
On 11/9/20 8:18 PM, Tom Rini wrote:
> On Mon, Nov 09, 2020 at 08:15:43PM +0100, Heinrich Schuchardt wrote:
>
>> On 11/9/20 7:54 PM, Heinrich Schuchardt wrote:
>>> The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
>>>
>>> Merge tag 'dm-pull5nov20' of git://git.denx.de/u-
Hi Heinrich,
[...]
>
> > > + */
> > > +#define TPM2_NUM_PCR_BANKS 16
> > > +
> > > +/* Definition of (UINT32) TPM2_CAP Constants */
> > > +#define TPM2_CAP_PCRS 0x0005U
> > > +#define TPM2_CAP_TPM_PROPERTIES 0x0006U
> > > +
> > > +/* Definition of (UINT32) TPM2_PT Constants */
> > > +#de
With commit 690079767803 ("cros_ec: Support keyboard scanning with
EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard
strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does
not understand this command. We need to reply with
-EC_RES_INVALID_COMMAND to force check_for_keys() to
On 09/11/2020 23:34, Heinrich Schuchardt wrote:
> With commit 690079767803 ("cros_ec: Support keyboard scanning with
> EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard
> strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does
> not understand this command. We need to reply w
On 11/9/20 10:13 PM, Alper Nebi Yasak wrote:
> On 09/11/2020 23:34, Heinrich Schuchardt wrote:
>> With commit 690079767803 ("cros_ec: Support keyboard scanning with
>> EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard
>> strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does
On 11/9/20 10:37 PM, Neil Armstrong wrote:
> Hi,
>
> On 09/11/2020 04:12, Jaehoon Chung wrote:
>> Core clock phase value is changed from 180' to 270'.
>> It's more stable than before.
>> - Odroidn-N2/C4 : Working fine with 52MHz
>> - VIM3 : Working fine with 52MHz
>>
>> Before this patch, Odroid-C
Hi,
On 11/9/20 11:10 PM, Mark Kettenis wrote:
>> From: Neil Armstrong
>> Date: Mon, 9 Nov 2020 14:37:09 +0100
>>
>> Hi,
>>
>> On 09/11/2020 04:12, Jaehoon Chung wrote:
>>> Core clock phase value is changed from 180' to 270'.
>>> It's more stable than before.
>>> - Odroidn-N2/C4 : Working fine wit
-Original Message-
From: Simon Glass
Sent: Saturday, November 7, 2020 1:33 PM
To: Duffin, CooperX
Cc: U-Boot Mailing List ; uboot-snps-...@synopsys.com;
Tom Rini ; Robert Beckett ;
Heiko Schocher ; Wolgang Denk ; Ian Ray
Subject: Re: [dwi2c PATCH v1] dwi2c add offsets to reads
Hi Co
On 11/9/20 11:23 PM, Neil Armstrong wrote:
> On 09/11/2020 15:10, Mark Kettenis wrote:
>>> From: Neil Armstrong
>>> Date: Mon, 9 Nov 2020 14:37:09 +0100
>>>
>>> Hi,
>>>
>>> On 09/11/2020 04:12, Jaehoon Chung wrote:
Core clock phase value is changed from 180' to 270'.
It's more stable tha
On Mon, Nov 09, 2020 at 07:54:38PM +0100, Heinrich Schuchardt wrote:
> The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
>
> Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06
> 11:27:14 -0500)
>
> are available in the Git repository at:
>
> http
On Mon, Nov 09, 2020 at 07:31:08PM +0530, Amit Singh Tomar wrote:
> after commit 4ab3817ff16a ("clk: fixed-rate: Enable DM_FLAG_PRE_RELOC flag")
> Cubieboard7 (based on actions S700 SoC) fails to boot.
>
> It is due to the fact that the default value of CONFIG_SYS_MALLOC_F_LEN
> (0x400)
> would
On Thu, Oct 08, 2020 at 03:14:17PM +0200, Marek Vasut wrote:
> In case there is an EEPROM attached to the KS8851 MAC and the EEPROM
> contains a valid MAC address, the MAC address is loaded into the NIC
> registers on power on. Read the MAC address out of the NIC registers
> and provide it to U-Bo
Hey all,
It's regular release day and I'm back on schedule, so here's -rc2.
There's a few small'ish things outstanding in my queue, and a queue of
things building up for -next already. I'm going to try and make sure
what I pull in, even when a clean-up, is as close as can be to the
obviously cor
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