Add qspi clock
Signed-off-by: Peng Fan
---
V2:
Split a single patch from
https://patchwork.ozlabs.org/project/uboot/patch/20200503125956.6244-1-peng@nxp.com/
drivers/clk/imx/clk-imx8mm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/cl
Fix clk set parent, so we could still have correct clocks after
parent changing.
Signed-off-by: Peng Fan
---
V2:
Split fix into a single patch of
https://patchwork.ozlabs.org/project/uboot/patch/20200503125956.6244-1-peng@nxp.com/
drivers/clk/imx/clk-imx8mm.c | 5 -
1 file changed,
The sequence of arguments should match the format string.
For printing unsigned numbers we should use %u.
Signed-off-by: Heinrich Schuchardt
---
drivers/crypto/fsl/jobdesc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/
The value 0 assigned to final is overwritten before ever being used.
Remove the assignment.
Signed-off-by: Heinrich Schuchardt
---
drivers/crypto/fsl/fsl_hash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
inde
If a file cannot be loaded, show an error message.
Set the EFI boot device only after successfully loading a file.
Signed-off-by: Heinrich Schuchardt
---
fs/fs.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/fs/fs.c b/fs/fs.c
index ad4caaeb1e..12fa5a6489 10064
Hi,
> -Original Message-
> From: Bin Meng
> Sent: Friday, June 26, 2020 6:50 PM
> To: Sagar Kadam
> Cc: U-Boot Mailing List ; Rick Chen
> ; Bin Meng ; Jagan Teki
> ; Pragnesh Patel
> ; Anup Patel ; Simon
> Glass ; Ye Li ; Peng Fan
> ; Sean Anderson
> Subject: Re: [PATCH v6 3/4] riscv: c
Hi Bin,
> -Original Message-
> From: Bin Meng
> Sent: Friday, June 26, 2020 6:50 PM
> To: Sagar Kadam
> Cc: U-Boot Mailing List ; Rick Chen
> ; Bin Meng ; Jagan Teki
> ; Pragnesh Patel
> ; Anup Patel ; Simon
> Glass ; Ye Li ; Peng Fan
> ; Sean Anderson
> Subject: Re: [PATCH v6 2/4] ucla
In the future if we have separate symbols for DM_SPI_FLASH and
SPL_DM_SPI_FLASH we will not always have function declarations available
for some DM calls. This in turn leads to build warnings but not
failures as the code isn't used and is discarded at link time.
Restructure things to not build cod
From: Bin Meng
test_efi_fit tests fail on RISC-V currently. This is due to the
RISC-V arch_fixup_fdt() checks the #size-cells of the root node
in order to correctly fix up the reserved memory node.
Update #size-cells to 1 so tests can pass.
Signed-off-by: Bin Meng
---
test/py/tests/test_efi_
From: Bin Meng
Change to use OpenSBI release v0.8 generic platform images for QEMU
RISC-V CI testing for azure, gitlab and travis-ci.
Signed-off-by: Bin Meng
---
Depends on the following 2 patches:
- "fdtdec: Honor #address-cells and #size-cells in fdtdec_add_reserved_memory()"
which is curre
+Andy Yan for this topic,
Hi Patrick and Arnaud,
I would like to leave this patch until the code fits for all the socs,
Thanks,
- Kever
On 2020/6/8 下午8:39, Patrick Wildt wrote:
On Mon, Jun 08, 2020 at 02:24:32PM +0200, Arnaud Patard wrote:
Patrick Wildt writes:
On Mon, Jun 08, 2020 a
Hi Kurt,
On 2020/6/4 上午5:17, Peter Geis wrote:
On Tue, Jun 2, 2020 at 11:12 AM Kurt Miller wrote:
On Tue, 2020-06-02 at 10:23 +0800, Shawn Lin wrote:
在 2020/6/2 9:59, Kever Yang 写道:
Hi Kurt,
On 2020/6/2 上午4:30, Kurt Miller wrote:
On at least the RockPro64, many cards will trip a
synchron
+Simon,
On Sat, Jun 27, 2020 at 8:00 PM Tom Rini wrote:
>
> In the future if we have separate symbols for DM_SPI_FLASH and
> SPL_DM_SPI_FLASH we will not always have function declarations available
> for some DM calls. This in turn leads to build warnings but not
> failures as the code isn't use
On 6/27/20 2:12 PM, Bin Meng wrote:
> From: Bin Meng
>
> test_efi_fit tests fail on RISC-V currently. This is due to the
> RISC-V arch_fixup_fdt() checks the #size-cells of the root node
> in order to correctly fix up the reserved memory node.
>
> Update #size-cells to 1 so tests can pass.
>
> Sig
On 2020/6/4 上午11:09, Kever Yang wrote:
On 2020/6/3 下午11:44, Marcin Juszkiewicz wrote:
With video output enabled and USB keyboard supported there is no need
for serial console. So let initialize USB subsystem so keyboard
connected to
board (either directly or via hub) can be used to interrup
Hi Tom,
On 2020/6/27 上午4:21, Tom Rini wrote:
On Thu, Jun 25, 2020 at 08:32:10PM +0530, Jagan Teki wrote:
On Mon, Jun 8, 2020 at 7:47 PM Jagan Teki wrote:
Add missing BOOTENV_SF command in rk3399 config.
Fix it.
Fixes: f263b860acf8 ("rk3399: Enable SF distro bootcmd")
Signed-off-by: Jagan Te
On 2020/6/8 下午10:17, Jagan Teki wrote:
Add missing BOOTENV_SF command in rk3399 config.
Fix it.
Fixes: f263b860acf8 ("rk3399: Enable SF distro bootcmd")
Signed-off-by: Jagan Teki
Reported-by: Suniel Mahesh
Tested-by: Suniel Mahesh
Reviewed-by: Kever Yang
Thanks,
- Kever
---
include/
On 2020/6/8 下午10:17, Jagan Teki wrote:
Add missing BOOTENV_SF command in rk3399 config.
Fix it.
Fixes: f263b860acf8 ("rk3399: Enable SF distro bootcmd")
Signed-off-by: Jagan Teki
Reported-by: Suniel Mahesh
Tested-by: Suniel Mahesh
Applied to u-boot-rockchip master branch.
---
include/c
On 2020/6/22 下午9:19, Alexander Kochetkov wrote:
Move the setting for noc remap out of SPL code. Changing
noc remap inside SPL results in breaking back to BROM
boot.
Fixes commit c14fe2a8e192 ("rockchip: rk3188: Move SoC
one time setting into arch_cpu_init()").
Signed-off-by: Alexander Kochetk
On 2020/6/22 下午9:19, Alexander Kochetkov wrote:
Move the setting for noc remap out of SPL code. Changing
noc remap inside SPL results in breaking back to BROM
boot.
Fixes commit c14fe2a8e192 ("rockchip: rk3188: Move SoC
one time setting into arch_cpu_init()").
Signed-off-by: Alexander Kochetk
+David,
Hi David,
Could you help to commend on this?
Hi Alex,
Thanks for your patch.
On 2020/6/22 下午9:06, Alexander Kochetkov wrote:
The commit e7ae4cf27a6d 'pinctrl: rockchip: Add common rockchip
pinctrl driver' dropped rk3188_pinctrl_request operation, that
did switching to new im
On 2020/6/9 上午6:50, Peter Robinson wrote:
Enable the rng so UEFI can provide entropy for KASLR
Signed-off-by: Peter Robinson
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi| 4
conf
On 2020/6/9 上午6:50, Peter Robinson wrote:
The built in keyboard on the Pinebook Pro is attached via USB so
fix this up to ensure USB works as expected.
Signed-off-by: Peter Robinson
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/pinebook-pro-rk3399_defconfig | 5 +
include/c
On 2020/6/9 上午6:50, Peter Robinson wrote:
Some minor fixes for SPI flash on the Pinebook Pro and also
default to saving environment to the SPI flash as it's
guaranteed to be on board.
Signed-off-by: Peter Robinson
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3399-pineboo
On 2020/6/10 下午6:36, Jagan Teki wrote:
VMARC RK3399Pro SOM is a standard SMARC SOM design with
Rockchip RK3399Pro SoC, which is designed by Vamrs.
Specification:
- Rockchip RK3399Pro
- PMIC: RK809-3
- SD slot, 16GiB eMMC
- 2xUSB-2.0, 1xUSB3.0
- USB-C for power supply
- Ethernet, PCIe
- HDMI, M
On 2020/6/10 下午6:36, Jagan Teki wrote:
Sync linux-next v5.7-rc1 rk3399pro.dtsi.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3399pro.dtsi | 22 ++
1 file changed, 22 insertions(+)
create mode 100644 arch/arm/dts/rk3399pro.d
On 2020/6/10 下午6:36, Jagan Teki wrote:
Rock Pi N10 is a Rockchip RK3399Pro based SBC, which has
- VMARC RK3399Pro SOM (as per SMARC standard) from Vamrs.
- Compatible carrier board from Radxa.
VAMRC RK3399Pro SOM need to mount on top of radxa dalang
carrier board for making Rock Pi N10 SBC.
S
On 2020/6/10 下午6:36, Jagan Teki wrote:
Carrier board often referred as baseboard. For making
complete SBC or any other industrial boards, these
carrier boards will be used with associated SOMs.
Radxa has Dalang carrier board which supports on-board
peripherals, ports like USB-2.0, USB-3.0, HDM
On 2020/6/16 上午7:30, Hugh Cole-Baker wrote:
SPL_ATF_NO_PLATFORM_PARAM is selected by default for RK3399 configs, to
guard against issues when used with TF-A versions that perform
insufficient validation on the platform parameter. However, since commit
8109f738ffa7 "rockchip: increase FDT buffer
On 2020/6/18 下午10:12, Jagan Teki wrote:
Enable USB3.0 Host support for RockPI-4 boards.
Note that the Upper USB3.0 port is marked as otg and
lower USB3.0 port marked as host, so this below log
capture when USB3.0 mass storage plug in at lower
USB 3.0 port.
Log:
Bus usb@fe38: USB EHCI 1.00
On 2020/6/18 下午10:12, Jagan Teki wrote:
Enable USB gadget for rock-pi-4 boards.
This would help to use fastboot by default.
Note: Connect the Host USB cable (Port A or C) to rock-pi-4
Upper USB 3.0 port.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for
On 2020/6/18 下午10:12, Jagan Teki wrote:
Enable PCI/NVME for M.2 Slot on RockPI-4 boards.
=> nvme info
Device 0: Vendor: 0x144d Rev: 2B2QEXM7 Prod: S4EUNG0MC10012Y
Type: Hard Disk
Capacity: 238475.1 MB = 232.8 GB (488397168 x 512)
Cc: Tom Cubie
Signed-off-by: Jagan T
On 2020/6/18 下午10:12, Jagan Teki wrote:
Enable DWC3 core, gadget for roc-rk3399-pc board.
This would help to use fastboot by default.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v2:
- rebase on master
configs/rock-pi-4-rk3399_defconfig | 6 ++
On 2020/6/18 下午10:12, Jagan Teki wrote:
Enable config options to get HDMI output on RockPI-4 boards.
Signed-off-by: Jagan Teki
---
Changes for v2:
- rebase on master
configs/rock-pi-4-rk3399_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs/rock-pi-4-rk3399_defco
On 2020/6/18 下午10:12, Jagan Teki wrote:
Adjust the ENV offset, size to fit into all images
on 16MB flash.
Signed-off-by: Jagan Teki
---
Changes for v2:
- rebase on master
configs/rock-pi-4-rk3399_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs/rock-pi-4-rk3399_
To make clear, there is kernel driver i2c-rk3x.c.
For rk3066 it write bits in the GRF word at offset 0x154. See [1] and [2].
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/i2c/busses/i2c-rk3x.c#n1236
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/torvald
On 2020/6/19 上午12:12, Jagan Teki wrote:
VMARC RK3288 SOM is a standard SMARC SOM design with
Rockchip RK3288 SoC, which is designed by Vamrs.
Specification:
- Rockchip RK3288
- PMIC: RK808
- SD slot, 16GiB eMMC
- 2xUSB-2.0, 1xUSB3.0
- USB-C for power supply
- Ethernet, PCIe
- HDMI, MIPI-DSI/CS
On 2020/6/19 上午12:12, Jagan Teki wrote:
Rock Pi N8 is a Rockchip RK3288 based SBC, which has
- VMARC RK3288 SOM (as per SMARC standard) from Vamrs.
- Compatible carrier board from Radxa.
VAMRC RK3288 SOM need to mount on top of radxa dalang
carrier board for making Rock Pi N8 SBC.
So, add ini
On 2020/6/19 上午12:12, Jagan Teki wrote:
Radxa dalang carrier boards are used to mount vmarc SoM's
of rk3399pro and rk3288 to make complete SBC.
Among these combinations, card detection gpio, max-frequency
properties are used with rk3399pro SoM but not required for
rk3288 SoM based on the hardw
On 2020/6/22 下午9:17, Alexander Kochetkov wrote:
The commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock
driver") changed ARM clock from 600MHz to 1600MHz. It made boot
unstable due to the fact that PMIC at the start generates insufficient
voltage for operation. See also: commit f4f57
Hi Alex,
I think it will be better to update the rk3188_clk_probe() function
instead of
what you have modified if the RK3188 and RK3188A has the same PLL(I'm
not sure
about it now).
Thanks,
- Kever
On 2020/6/22 下午9:17, Alexander Kochetkov wrote:
Empirically, I found that DPLL on rk
Hi Kever,
Strange… Then I tested a year ago I saw, that writing into bwadj registers had
no effect
for some PLLs. But now I did another test. See patch and output. Looks like
rk3188 allow
writing into bwadj fields.
So I do something like 'priv->has_bwadj = 1' in the rk3188_clk_probe() and
se
On 6/25/20 2:19 PM, Michael Walle wrote:
> If it is already instantiated tear it down first and then reinstanciate
> it again with prediction resistance.
>
> Signed-off-by: Michael Walle
> ---
> drivers/crypto/fsl/desc.h| 2 ++
> drivers/crypto/fsl/jobdesc.c | 12 ++-
> drivers/crypto/fs
Am 2020-06-26 18:26, schrieb Heinrich Schuchardt:
On 6/25/20 11:01 PM, Michael Walle wrote:
Am 2020-06-25 18:03, schrieb Heinrich Schuchardt:
On 25.06.20 16:36, Heinrich Schuchardt wrote:
On 25.06.20 14:18, Michael Walle wrote:
First, improve the compatibility on newer Era CAAMs. These
introd
Am 2020-06-26 18:26, schrieb Heinrich Schuchardt:
On 6/25/20 11:01 PM, Michael Walle wrote:
Am 2020-06-25 18:03, schrieb Heinrich Schuchardt:
On 25.06.20 16:36, Heinrich Schuchardt wrote:
On 25.06.20 14:18, Michael Walle wrote:
First, improve the compatibility on newer Era CAAMs. These
introd
From: Dennis Gilmore
The helios4 is built on the same microsom as the clearfog, by syncing the config
we enable the same featureset that exists in the som on the helios4. The current
config does not boot as some of the clearfog changes needed to be made on the
helios4 also, generally speaking mos
Align the status line with all the other output in U-Boot.
Before the change:
DDR3.9 GiB (DDR3, 32-bit, CL=11, ECC on)
SEC0: RNG instantiated
WDT: Started with servicing (60s timeout)
After the change:
DDR3.9 GiB (DDR3, 32-bit, CL=11, ECC on)
SEC0: RNG instantiated
WDT: Started with
We need the era in other modules, too. For example, to get the RNG
version.
Signed-off-by: Michael Walle
Reviewed-by: Horia Geantă
---
drivers/crypto/fsl/sec.c | 10 +-
include/fsl_sec.h| 2 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/fsl/se
Since Era 10, the version registers changed. Add the version registers
and use them on newer modules.
Signed-off-by: Michael Walle
Reviewed-by: Horia Geantă
---
drivers/crypto/fsl/jr.c | 12 --
include/fsl_sec.h | 51 +++--
2 files changed, 54 i
If it is already instantiated tear it down first and then reinstanciate
it again with prediction resistance.
Signed-off-by: Michael Walle
---
drivers/crypto/fsl/desc.h| 2 ++
drivers/crypto/fsl/jobdesc.c | 12 ++-
drivers/crypto/fsl/jobdesc.h | 2 ++
drivers/crypto/fsl/jr.c | 67 +
The secure keys (TDKEK, JDKEK, TDSK) can only be generated once after a
POR. Otherwise the RNG4 will throw an error.
Signed-off-by: Michael Walle
Reviewed-by: Horia Geantă
---
drivers/crypto/fsl/jobdesc.c | 4 ++--
drivers/crypto/fsl/jobdesc.h | 2 +-
drivers/crypto/fsl/jr.c | 9 +
Register the random number generator with the rng subsystem in u-boot.
This way it can be used by EFI as well as for the 'rng' command.
Signed-off-by: Michael Walle
---
drivers/crypto/fsl/Kconfig | 14 ++
drivers/crypto/fsl/Makefile | 1 +
drivers/crypto/fsl/jobdesc.c | 10
drivers/
First, improve the compatibility on newer Era CAAMs. These introduced new
version registers. Secondly, add RNG support for the CAAM. This way we get
random number generator support for EFI for free and KASLR will work with
ARM64 kernels booted with bootefi.
Changes since v3:
- use private data in
On 6/27/20 10:58 PM, Michael Walle wrote:
> Register the random number generator with the rng subsystem in u-boot.
> This way it can be used by EFI as well as for the 'rng' command.
>
> Signed-off-by: Michael Walle
Tested on a i.MX6 Wandward Quad with additional patch
ARM: mx6: make CAAM usable
From: Ye Li
Update video bmp code so that we can display 8 bits logo on
24 or 32 bpp framebuffer.
Signed-off-by: Ye Li
Signed-off-by: Anatolij Gustschin
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki # bpi-m1+, bpi-m64
---
Changes in v2:
- reduce code
- update commit message
drivers/video
Hi Heinrich,
On Sat, Jun 27, 2020 at 9:43 PM Heinrich Schuchardt wrote:
>
> On 6/27/20 2:12 PM, Bin Meng wrote:
> > From: Bin Meng
> >
> > test_efi_fit tests fail on RISC-V currently. This is due to the
> > RISC-V arch_fixup_fdt() checks the #size-cells of the root node
> > in order to correctly
From: Bin Meng
test_efi_fit tests fail on RISC-V currently. This is due to the
RISC-V arch_fixup_fdt() checks the #size-cells of the root node
in order to correctly fix up the reserved memory node.
Per the DT binding, the /reserved-memory node requires both
<#address-cells> and <#size-cells> and
On 2020/6/8 上午2:36, Patrick Wildt wrote:
The EDP_LCDC_SEL bit has to be set correctly to select vop0 or
vop1, but so far we have set it in both conditions, which is not
correct.
Can someone verify this is the correct way round? vop1 -> set,
vop0 -> clear?
Signed-off-by: Patrick Wildt
I wi
Hi :
On 6/27/20 8:56 PM, Kever Yang wrote:
+Andy Yan for this topic,
Hi Patrick and Arnaud,
I would like to leave this patch until the code fits for all the
socs,
Thanks,
- Kever
On 2020/6/8 下午8:39, Patrick Wildt wrote:
On Mon, Jun 08, 2020 at 02:24:32PM +0200, Arnaud Patard wrote:
HI Jagan,
On 2020/6/18 下午11:39, Jagan Teki wrote:
reset cause is a generic functionality based on the soc
cru registers in rockchip. This can be used for printing
the cause of reset in cpuinfo or some other place where
reset cause is needed.
Other than cpuinfo, reset cause can also be using dur
On 2020/6/18 下午11:39, Jagan Teki wrote:
roc-rk3399-pc has some specific requirements to support LEDS,
environment. board detection and etc prior to U-Boot proper.
So as of now SPL would be a better stage for these custom board
requirements to support unlike TPL. Adding few of these custom
requ
Hi Jagan,
On 2020/6/18 下午11:39, Jagan Teki wrote:
Usually printing the SPL banner varies between architecture
or board codes.
- Some would print before relocation at the end board_init_f
for making sure all initialization prior to this would happen
properly. if at all there is a requiremen
Hi Jagan,
On 2020/6/18 下午11:39, Jagan Teki wrote:
spl_board_init is a proper location and common practice
option to have a custom board initialization code after
relocation in SPL.
This patch add the feasibility to add the custom SPL board
initzlaization throughout rockchip platforms and adjust
On Mon, Jun 15, 2020 at 1:00 AM Simon Glass wrote:
>
> Update this code to use livetree calls instead of flat-tree.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Wolfgang Wallner
> ---
>
> (no changes since v1)
>
> arch/x86/cpu/mp_init.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
On Mon, Jun 15, 2020 at 1:00 AM Simon Glass wrote:
>
> At present the 'flight plan' for CPUs is passed into mp_init. But it is
> always the same. Move it into the mp_init file so everything is in one
> place. Also drop the SMI function since it does nothing. If we implement
> SMIs, more refactorin
On Mon, Jun 15, 2020 at 1:00 AM Simon Glass wrote:
>
> These parameters are named differently from elsewhere in this file. Switch
> them to avoid confusion.
>
> Also add comments to this function.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2:
> - Add comments to explain what start_aps()
Hi Simon,
On Mon, Jun 15, 2020 at 1:00 AM Simon Glass wrote:
>
> This does not need to be global across all functions in this file. Pass a
> parameter instead.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Wolfgang Wallner
> ---
>
> (no changes since v1)
>
> arch/x86/cpu/mp_init.c | 22 +++
On Mon, Jun 15, 2020 at 1:00 AM Simon Glass wrote:
>
> The functions used by the flight plan are declared in the header file but
> are not used in any other file.
>
> Move the flight plan steps down to just above where it is used so that we
> can make these function static.
>
> Signed-off-by: Simo
On Mon, Jun 15, 2020 at 1:00 AM Simon Glass wrote:
>
> Fix a typo in the command help.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Wolfgang Wallner
> ---
>
> (no changes since v1)
>
> cmd/x86/mtrr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng
On Mon, Jun 15, 2020 at 1:00 AM Simon Glass wrote:
>
> Drop some #ifdefs that are not needed or can be converted to compile-time
> checks.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Wolfgang Wallner
> ---
>
> (no changes since v1)
>
> arch/x86/cpu/cpu.c | 58
Hi Simon,
On Mon, Jun 15, 2020 at 1:00 AM Simon Glass wrote:
>
> At present the APs (non-boot CPUs) are inited once and then parked ready
> for the OS to use them. However in some cases we want to send new requests
> through, such as to change MTRRs and keep them consistent across CPUs.
>
> Chang
On Mon, Jun 15, 2020 at 1:00 AM Simon Glass wrote:
>
> At present each CPU is given a number when it starts itself up. While this
> saves a tiny amount of time by doing the device-tree read in parallel, it
> is confusing that the numbering happens on the fly.
>
> Move this code into mp_init() and
On Mon, Jun 15, 2020 at 1:00 AM Simon Glass wrote:
>
> This function is misnamed since it does not actually init the BSP. Also
> it is convenient to adjust it to return a little more information.
>
> Rename and update the function, to allow it to return the BSP CPU device
> and number, as well as
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