Hi Kever,
On Fri, May 22, 2020 at 8:45 AM Kever Yang wrote:
>
> Hi Jagan,
>
> On 2020/5/10 上午12:56, Jagan Teki wrote:
> > Due to board limitation some SSD's would work
> > on rock960 PCIe M.2 only with 1.8V IO domain.
> >
> > So, this patch enables grf io_sel explicitly to
> > make PCIe/M.2 to wo
Due to board limitation some SSD's would work
on rock960 PCIe M.2 only with 1.8V IO domain.
So, this patch enables grf io_sel explicitly to
make PCIe/M.2 to work.
Cc: Tom Cubie
Acked-by: Manivannan Sadhasivam
Signed-off-by: Jagan Teki
---
Changes for v4:
- Add missing header bitops.h
board/v
Hi Simon,
Am 2020-05-22 04:34, schrieb Simon Glass:
Hi Michael,
On Thu, 21 May 2020 at 17:28, Michael Walle wrote:
Am 2020-05-21 16:13, schrieb Bin Meng:
> On Thu, May 21, 2020 at 12:40 AM Michael Walle
> wrote:
>>
>> It is possible to specify a device tree node for an USB device. This
>> i
In Commit d64077202158 ("spi: cadence_qspi: Move to spi-mem framework")
it removes setting to quad write bit by accident. This commit restores
it back and also adding checking for octal support.
Fixes: d64077202158 ("spi: cadence_qspi: Move to spi-mem framework")
Signed-off-by: Ley Foon Tan
---
On 16/05/20 9:05 pm, Faiz Abbas wrote:
> From: Andreas Dannenberg
>
> When the boot of J721E devices using the primary bootmode (configured
> via device pins) fails a boot using the configured backup bootmode is
> attempted. To take advantage of the backup boot mode feature go ahead
> and add
search for gpio label if gpio name from bankname is not found.
This makes sense on boards with different hardware verions. You
can now search for the gpio label name, and can give the gpio
a unique name. The real gpio pin number is not needed in board
code anymore.
while at it add basic gpio hog
save the GPIOD_ flags also in the gpio descriptor.
Signed-off-by: Heiko Schocher
Reviewed-by: Patrick Delaunay
Fixes: 788ea834124b ("gpio: add function _dm_gpio_set_dir_flags")
---
Changes in v6:
- add reviewed by from Patrick and Fixes tag
Changes in v5:
- add comment from patrick, update th
dm_gpio_lookup_name() searches for a gpio through
the bank name. But we have also gpio labels, and it
makes sense to search for a gpio also in the labels
we have defined, if no gpio is found through the
bank name definition.
This is useful for example if you have a wp pin on
different gpios on dif
currently gpio hog function is not tested with "ut dm gpio"
so add some basic tests for gpio hog functionality.
For this enable GPIO_HOG in sandbox_defconfig, add
in DTS some gpio hog entries, and add testcase in
"ut dm gpio" command.
Signed-off-by: Heiko Schocher
Reviewed-by: Simon Glass
---
On Wed, May 20, 2020 at 7:45 AM Thomas Fitzsimmons wrote:
>
> Hi Rayagonda and Vikas,
>
> Rayagonda Kokatanur writes:
>
> > From: Vikas Gupta
> >
> > Add optee based bnxt fw load driver.
>
> What is "bnxt"? Maybe you could add a comment explaining what it is, or
> at least expanding it if it's
Hi Simon,
On Fri, May 22, 2020 at 12:51 AM Simon Glass wrote:
>
> Hi,
>
> On Tue, 19 May 2020 at 20:15, Thomas Fitzsimmons wrote:
> >
> > Hi Rayagonda and Vikas,
> >
> > Rayagonda Kokatanur writes:
> >
> > > From: Vikas Gupta
> > >
> > > Add optee based bnxt fw load driver.
> >
> > What is "bn
On 5/20/20 2:22 PM, Tom Rini wrote:
> On Thu, May 07, 2020 at 08:36:03PM +0200, Jan Kiszka wrote:
>
>> From: Jan Kiszka
>>
>> This driver is safe to use in SPL without relocation. Denying
>> DM_FLAG_PRE_RELOC prevents its usability for verifying the main U-Boot
>> or other artifacts from the SPL u
Hi,
this patchset adding support for Tap delay programming for ZynqMP and
Versal.
Based on mainline discussion also DT properties have been introduced which
are documented here.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/Documentation/devicetree/bindings/mmc/mmc-cont
From: Ashok Reddy Soma
This reverts commit 942b5fc03218d1c94468fc658e7dec65dabcc830.
This is partial revert of the above commit.
mmc_of_parse() is reading no-1-8-v from device tree and if set,
it is clearing the UHS speed capabilities of cfg->host_caps.
cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_H
From: Ashok Reddy Soma
Define timing macro's for all the available speeds of mmc. This is
done similar to linux. Replace other macro's used in zynq_sdhci.c
with these new macro's.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
drivers/mmc/zynq_sdhci.c | 24 +++---
Just group macros below headers. Other patches will be using this location
too.
Signed-off-by: Michal Simek
---
drivers/mmc/zynq_sdhci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 02583f76f936..1c83aab84021 1
Define input and output clock phase delays with pre-defined values.
Define arasan_sdhci_clk_data type structure and add it to priv
structure and store these clock phase delays in it.
Read input and output clock phase delays from dt. If these values are
not passed through dt, use pre-defined value
From: Ashok Reddy Soma
Define and use functions for setting input and output tapdelays
based on clk phase delays.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
drivers/mmc/zynq_sdhci.c | 128 +--
1 file changed, 123 insertions(+), 5 delet
From: Ashok Reddy Soma
Fix the condition to set UHS timings for speeds upto HS200.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
drivers/mmc/zynq_sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
From: Ashok Reddy Soma
Define default values for input and output clock phase delays for
Versal. Also define functions for setting tapdelays based on these
clock phase delays.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
drivers/mmc/zynq_sdhci.c | 160 +
On 22.05.20 12:42, Heinrich Schuchardt wrote:
> On 5/20/20 2:22 PM, Tom Rini wrote:
>> On Thu, May 07, 2020 at 08:36:03PM +0200, Jan Kiszka wrote:
>>
>>> From: Jan Kiszka
>>>
>>> This driver is safe to use in SPL without relocation. Denying
>>> DM_FLAG_PRE_RELOC prevents its usability for verifyin
On Thu, May 21, 2020 at 08:23:04PM -0600, Simon Glass wrote:
> At present MTRRs are mirrored to the secondary CPUs only once, as those
> CPUs are started up. But U-Boot may add more MTRRs later, e.g. if it
> decides that a video console must be set up.
>
> This series enhances the x86 multi-proces
Am May 22, 2020 10:50:29 AM UTC schrieb Jan Kiszka :
>On 22.05.20 12:42, Heinrich Schuchardt wrote:
>> On 5/20/20 2:22 PM, Tom Rini wrote:
>>> On Thu, May 07, 2020 at 08:36:03PM +0200, Jan Kiszka wrote:
>>>
From: Jan Kiszka
This driver is safe to use in SPL without relocation. Denyi
Although I think it never occurs, the code doesn't make sense, because
it may allow to assign an IN endpoint to ss->ep_out.
Signed-off-by: Hayes Wang
---
drivers/usb/eth/r8152.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/eth/r8152.c b/drivers/u
As reported by Nicolas Carrier on the Buildroot mailing list [1],
there is a new build issue while building a program which interacts with
the u-boot environment. This program uses the headers of the ubootenv
library provided by uboot-tools.
This is a recent change from uboot [2] adding "#include
These are minor corrections for r8152 driver.
Hayes Wang (2):
eth/r8152: fix assigning the wrong endpoint
eth/r8152: fix typo in register name
drivers/usb/eth/r8152.c | 22 --
drivers/usb/eth/r8152.h | 4 ++--
2 files changed, 14 insertions(+), 12 deletions(-)
--
2.21.
Hi All,
I have applied Jagan's PCIe patch for Rockchip (
http://lists.infradead.org/pipermail/linux-rockchip/2020-May/031117.html)
to my Rock Pi 4 but I am getting intermittent results with the PCIe bus
(and hence NVMe m.2) showing in u-boot (and then Linux).
When it is successful the pci command
> -Original Message-
> From: Peng Fan
> Sent: 2020年5月19日 11:38
> To: BOUGH CHEN ; u-boot@lists.denx.de
> Cc: dl-uboot-imx
> Subject: RE: [PATCH] mmc: retry CMD1 in mmc_send_op_cond() until the
> eMMC is ready
>
> > Subject: [PATCH] mmc: retry CMD1 in mmc_send_op_cond() until the eMMC
> >
The PAL_BDC_CR should be PLA_BDC_CR.
Signed-off-by: Hayes Wang
---
drivers/usb/eth/r8152.c | 8
drivers/usb/eth/r8152.h | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c
index 7c48663370..f201a1789b 100644
--- a/dr
unzip calls gzwrite() which is provided in lib/gunzip.c. Make sure it is
automatically pulled in if the user selects CMD_UNZIP.
Signed-off-by: Michael Walle
---
cmd/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index f9be1988f6..f4eb575b6e 100644
--- a/cmd
Automatically pull in the needed libraries for zip and unzip. Move the
CONFIG_GZIP_COMPRESSED from legacy config.h style to a Kconfig option. The
sole user of CONFIG_GZIP_COMPRESSED is the sandbox target for the
compression tests. Remove the CONFIG option in its config.h and instead
select it toget
Fix the following warning:
cmd/zip.c: In function ‘do_zip’:
cmd/zip.c:30:6: warning: implicit declaration of function ‘gzip’; did you mean
‘do_zip’? [-Wimplicit-function-declaration]
if (gzip((void *) dst, &dst_len, (void *) src, src_len) != 0)
^~~~
do_zip
Include gzip.h header whi
Move the CONFIG_GZIP_COMPRESSED from a config.h macro to a Kconfig menu
item. It is not selectable by a user because there is no reason to do
so. Instead it will be automatically selected by the stuff which uses
gzip(), like the zip command.
Remove it from the config_whitelist.txt. Also remove
CON
CONFIG_BZIP2 and CONFIG_GZIP_COMPRESSED are Kconfig options. Select them
by CONFIG_SANDBOX instead of setting them in configs/sandbox.h.
Signed-off-by: Michael Walle
---
arch/Kconfig | 2 ++
include/configs/sandbox.h | 3 ---
2 files changed, 2 insertions(+), 3 deletions(-)
diff --
On Mon, 11 May 2020 12:04:32 -0400
Tom Rini tr...@konsulko.com wrote:
> On Mon, May 11, 2020 at 12:29:37PM +0200, Stefano Babic wrote:
>
> > Hi Tom,
> >
> > please pull these i.MX's changes for 2020.07, thanks !
> >
> > The following changes since commit c5c657644bc35fd6b3d6e5517698721e90646b8d
Hi list,
> I want to use the ums command to access the SD card of a
> A20-OlinuxIno-Lime
> board via usb-org cable. For that I start the CPU in FEL mode, download
> the
> u-boot-sunxi-with-spl.bin file by sunxi-fel tool. I do this FEL mode boot
> for
> preparation of an Einstein A20 board, which
Hi Heiko,
Thanks for your response.
On 5/22/20, Heiko Schocher wrote:
>> Are there any ways or tools in Linux to change MTD settings (most
>> likely the ECC or DTB) to the same setting in u-boot? I do have mtd
>> and fw_setenv in Linux.
>
> No for U-Boot (as I am aware of). You need to fix the D
On 22.05.20 13:38, Heinrich Schuchardt wrote:
> Am May 22, 2020 10:50:29 AM UTC schrieb Jan Kiszka :
>> On 22.05.20 12:42, Heinrich Schuchardt wrote:
>>> On 5/20/20 2:22 PM, Tom Rini wrote:
On Thu, May 07, 2020 at 08:36:03PM +0200, Jan Kiszka wrote:
> From: Jan Kiszka
>
> Thi
> From: Anthony Davies
> Date: Fri, 22 May 2020 10:49:12 +1000
>
> Hi All,
>
> I have applied Jagan's PCIe patch for Rockchip (
> http://lists.infradead.org/pipermail/linux-rockchip/2020-May/031117.html)
> to my Rock Pi 4 but I am getting intermittent results with the PCIe bus
> (and hence NVMe
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode.
If the device tree provides a read delay value, use that directly and do
not perform the calibration procedure.
This allows the device tree to over-ride the read delay value in cases
where the read delay value obtained via calibration is incorrect. One
such example is the Cypress Semper flash. It
Set up opcode extension and enable/disable DTR mode based on whether the
command is DTR or not.
xSPI flashes can have a 4-byte dummy address associated with some
commands like the Read Status Register command in octal DTR mode. Since
the flash does not support sending the dummy address, we can not
Hi,
This series adds support for octal DTR flashes in the spi-nor framework,
and then adds hooks for the Cypress Semper flash which is an xSPI
compliant Octal DTR flash.
The Cadence QSPI controller driver is also updated to run in Octal DTR
mode.
Tested on TI J721e EVM.
Changes in v4:
- Fix BFP
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index d
nor->setup() can be used by flashes to configure settings in case they
have any peculiarities that can't be easily expressed by the generic
spi-nor framework. This includes things like different opcodes, dummy
cycles, page size, uniform/non-uniform sector sizes, etc.
Move related declarations to a
These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 224
This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
the number of dummy cycles needed for a Read Status Register command,
and the number of address bytes needed for a Read Status Register
command.
The default d
The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.
Rework the hwcaps selection logic to use spi_mem_supports_op().
Based on
Some devices in DTR mode expect an extra command byte called the
extension. The extension can either be same as the opcode, bitwise
inverse of the opcode, or another additional byte forming a 16-byte
opcode. Get the extension type from the BFPT. For now, only flashes with
"repeat" and "inverse" ext
Sometimes the information in a flash's SFDP tables is wrong. Sometimes
some information just can't be expressed in the SFDP table. So,
introduce the fixup hooks to allow tailoring settings for a specific
flash.
Three hooks are added: default_init, post_sfdp, and post_bfpt. These
allow tweaking the
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 31 +++
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 33 insertions(
The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").
While this is technically incorrect, it is not reason enough to abort
BFPT parsing. Instead
The xSPI Profile 1.0 table specifies how many dummy cycles and address
bytes are needed for the Read Status Register command in Octal DTR mode.
Use that information to send the correct Read SR command.
Some controllers might have trouble reading just 1 byte in DTR mode. So,
when we are in DTR mode
Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All
On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it
supports it. But Linux as of now expects to get the flash in 1S-1S-1S
mode. Handing the flash to Linux in Octal DTR mode means the kernel will
fail to detect the flash.
So, we need to reset to Power-on-Reset (POR) state before hand
When the flash is handed to us in a stateful mode like 8D-8D-8D, it is
difficult to detect the mode the flash is in. One option is to read SFDP
in all modes and see which one gives the correct "SFDP" signature, but
not all flashes support SFDP in 8D-8D-8D mode.
Further, even if you detect the mode
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.
The SFDP programming on some older version
A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 6 ++
include/linux/mtd/spi-n
JESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to
reflect that.
The check for rev A or later compared the BFPT header length with the
maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so
was the BFPT length for both rev A and B, this check worked fine. But
now,
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
The flash supports the soft reset
2fa581ba910368d0f7f995fb906d6c5e4218b594:
Merge git://git.denx.de/u-boot-sh (2020-05-21 08:26:40 -0400)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git
tags/u-boot-rockchip-20200522
for you to fetch changes up to
> https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git
> tags/u-boot-rockchip-20200522
>
> for you to fetch changes up to 33863f744d513f5c16a254870e7b3cef8580bbc9:
>
> rockchip: rk3328: rock64 - fix gen3 SPL hang (2020-05-22 20:53:20 +0800)
>
> ---
On 5/22/20 10:54 AM, Hayes Wang wrote:
> The PAL_BDC_CR should be PLA_BDC_CR.
>
> Signed-off-by: Hayes Wang
> ---
> drivers/usb/eth/r8152.c | 8
> drivers/usb/eth/r8152.h | 4 ++--
> 2 files changed, 6 insertions(+), 6 deletions(-)
Applied, thanks. Take a look at 1/2 and resend it if a
On 5/22/20 10:54 AM, Hayes Wang wrote:
> Although I think it never occurs, the code doesn't make sense, because
> it may allow to assign an IN endpoint to ss->ep_out.
>
> Signed-off-by: Hayes Wang
> ---
> drivers/usb/eth/r8152.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions
Hi Andy,
On Fri, 22 May 2020 at 04:55, Andy Shevchenko
wrote:
>
> On Thu, May 21, 2020 at 08:23:04PM -0600, Simon Glass wrote:
> > At present MTRRs are mirrored to the secondary CPUs only once, as those
> > CPUs are started up. But U-Boot may add more MTRRs later, e.g. if it
> > decides that a vi
Hi Michael,
On Fri, 22 May 2020 at 01:32, Michael Walle wrote:
>
> Hi Simon,
>
> Am 2020-05-22 04:34, schrieb Simon Glass:
> > Hi Michael,
> >
> > On Thu, 21 May 2020 at 17:28, Michael Walle wrote:
> >>
> >> Am 2020-05-21 16:13, schrieb Bin Meng:
> >> > On Thu, May 21, 2020 at 12:40 AM Michael W
Hi Marek,
On Thu, 21 May 2020 at 23:56, Marek Szyprowski wrote:
>
> Hi Simon,
>
> On 19.05.2020 18:47, Simon Glass wrote:
> > On Tue, 19 May 2020 at 06:00, Marek Szyprowski
> > wrote:
> >> On 19.05.2020 00:38, Simon Glass wrote:
> >>> On Mon, 18 May 2020 at 07:18, Marek Szyprowski
> >>> wrote
On Tue, 19 May 2020 17:10:35 -0600
Simon Glass s...@chromium.org wrote:
> At present these functions fail silently even when debugging, which is not
> very helpful. Add a way to print a message to the serial output when an
> error is detected.
>
> Signed-off-by: Simon Glass
Reviewed-by: Anatoli
On Tue, 19 May 2020 17:10:36 -0600
Simon Glass s...@chromium.org wrote:
> Add a devicetree property to select a rotated console. This uses the same
> encoding as vidconsole itself: 0=normal; 1=90 degrees clockwise, 2=upside
> down, 3=90 degrees anticlockwise.
>
> Signed-off-by: Simon Glass
Revi
On Tue, 19 May 2020 17:10:37 -0600
Simon Glass s...@chromium.org wrote:
> The functions in this file do similar things but not always in the same
> way. To make the code easier to read and compare, use a separate 'linenum'
> variable in every function. This is then multiplied by the line length to
On Tue, 19 May 2020 17:10:38 -0600
Simon Glass s...@chromium.org wrote:
> At present when the console is rotated 180 degrees it starts almost a
> whole character to the left of the right edge (typically 7 pixels with
> an 8-pixel-wide font). On a display which aligns with the font width,
> this ju
On Tue, 19 May 2020 17:10:39 -0600
Simon Glass s...@chromium.org wrote:
> All of the functions in this file only apply if DM_VIDEO is enabled. Drop
> the #ifdef as it just clutters things up. Add the needed forward
> declaration.
>
> Signed-off-by: Simon Glass
Reviewed-by: Anatolij Gustschin
On Tue, 19 May 2020 17:10:40 -0600
Simon Glass s...@chromium.org wrote:
> Add a few notes to explain the purpose of each member of this struct.
>
> Signed-off-by: Simon Glass
Reviewed-by: Anatolij Gustschin
From: Heiko Stuebner
When calculating rrtmp/rr rsa_gen_key_prop() tries to make
(((rlen + 31) >> 5) + 1) steps in the rr uint32_t array and
(((rlen + 7) >> 3) + 1) / 4 steps in uint32_t rrtmp[]
with rlen being num_bits * 2
On a 4096bit key this comes down to to 257 uint32_t elements
in rr and 25
From: Heiko Stuebner
The exponent field of struct key_prop gets allocated an uint64_t,
and the contents are positioned from the back, so an exponent of
"0x01 0x00 0x01" becomes 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1"
Right now rsa_gen_key_prop() allocates a uint64_t but sets exp_len
to the size returne
From: Heiko Stuebner
padding_pss_verify only works with the default pss salt setting of -2
(length to be automatically determined based on the PSS block structure)
not -1 (salt length set to the maximum permissible value), which makes
verifications of signatures with that saltlen fail.
Until thi
From: Heiko Stuebner
rsa-checsum needs support for hash functions or else will run into
compile errors like:
u-boot/lib/rsa/rsa-checksum.c:28: undefined reference to
`hash_progressive_lookup_algo'
So similar to the main FIT_SIGNATURE entry selects HASH,
select SPL_HASH_SUPPORT for SPL_FIT_SIGNA
From: Heiko Stuebner
While the SPL may want to do signature checking this won't be
the case for TPL in all cases, as TPL is mostly used when the
amount of initial memory is not enough for a full SPL.
So on a system where SPL uses DM but TPL does not we currently
end up with a TPL compile error o
From: Heiko Stuebner
n, rr and rrtmp are used for internal calculations, but in the end
the results are copied into separately allocated elements of the
actual key_prop, so the n, rr and rrtmp elements are not used anymore
when returning from the function and should of course be freed.
Signed-of
From: Heiko Stuebner
Verifying FIT images obviously needs the rsa parts of crypto
support and while main uboot always compiles crypto support,
it's optional for SPL and we should thus select the necessary
option to not end up in compile errors like:
u-boot/lib/rsa/rsa-verify.c:328: undefined
From: Heiko Stuebner
Right now in multiple places there are only checks for the full
CONFIG_RSA_VERIFY_WITH_PKEY option, not split into main,spl,tpl variants.
This breaks when the rsa functions get enabled for SPL, for example to
verify u-boot proper from spl.
So fix this by using the existing
As an additional step to move documentation to doc/boards/rockchip
improve format of the supported board list to make it more readable.
Additionally, add the configuration files used to build them based on
doc/README.rockchip.
Signed-off-by: Walter Lozano
---
doc/board/rockchip/rockchip.rst | 68
As an additional step in the process of improve the Rockchip documentation
and based on the comments from [1] move the list of supported boards and
configs to doc/board/rockchip.
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=177974
Walter Lozano (3):
doc: board: rockchip: Improve
Update the list of supported boards with the information available
on doc/README.rockchip.
Signed-off-by: Walter Lozano
---
doc/board/rockchip/rockchip.rst | 16
1 file changed, 16 insertions(+)
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
inde
As documentation is being moved to doc/boards/rockchip create a warning
message and remove the redundant list of supported boards.
Signed-off-by: Walter Lozano
---
doc/README.rockchip | 72 +++--
1 file changed, 4 insertions(+), 68 deletions(-)
diff --git
From: Heiko Stuebner
The exponent field of struct key_prop gets allocated an uint64_t,
and the contents are positioned from the back, so an exponent of
"0x01 0x00 0x01" becomes 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1"
Right now rsa_gen_key_prop() allocates a uint64_t but sets exp_len
to the size returne
From: Heiko Stuebner
n, rr and rrtmp are used for internal calculations, but in the end
the results are copied into separately allocated elements of the
actual key_prop, so the n, rr and rrtmp elements are not used anymore
when returning from the function and should of course be freed.
Signed-of
From: Heiko Stuebner
padding_pss_verify only works with the default pss salt setting of -2
(length to be automatically determined based on the PSS block structure)
not -1 (salt length set to the maximum permissible value), which makes
verifications of signatures with that saltlen fail.
Until thi
From: Heiko Stuebner
Right now in multiple places there are only checks for the full
CONFIG_RSA_VERIFY_WITH_PKEY option, not split into main,spl,tpl variants.
This breaks when the rsa functions get enabled for SPL, for example to
verify u-boot proper from spl.
So fix this by using the existing
From: Heiko Stuebner
While the SPL may want to do signature checking this won't be
the case for TPL in all cases, as TPL is mostly used when the
amount of initial memory is not enough for a full SPL.
So on a system where SPL uses DM but TPL does not we currently
end up with a TPL compile error o
From: Heiko Stuebner
Verifying FIT images obviously needs the rsa parts of crypto
support and while main uboot always compiles crypto support,
it's optional for SPL and we should thus select the necessary
option to not end up in compile errors like:
u-boot/lib/rsa/rsa-verify.c:328: undefined
From: Heiko Stuebner
When calculating rrtmp/rr rsa_gen_key_prop() tries to make
(((rlen + 31) >> 5) + 1) steps in the rr uint32_t array and
(((rlen + 7) >> 3) + 1) / 4 steps in uint32_t rrtmp[]
with rlen being num_bits * 2
On a 4096bit key this comes down to to 257 uint32_t elements
in rr and 25
From: Heiko Stuebner
rsa-checsum needs support for hash functions or else will run into
compile errors like:
u-boot/lib/rsa/rsa-checksum.c:28: undefined reference to
`hash_progressive_lookup_algo'
So similar to the main FIT_SIGNATURE entry selects HASH,
select SPL_HASH_SUPPORT for SPL_FIT_SIGNA
From: Heiko Stuebner
rsa_verify() expects a memory region and wants to do the hashing itself,
but there may be cases where the hashing is done via other means,
like hashing a squashfs rootfs.
So add rsa_verify_hash() to allow verifiying a signature against
an existing hash. As this entails the s
> On 22.05.2020, at 16:13, Heiko Stuebner wrote:
>
> From: Heiko Stuebner
>
> The exponent field of struct key_prop gets allocated an uint64_t,
> and the contents are positioned from the back, so an exponent of
> "0x01 0x00 0x01" becomes 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1"
>
> Right now rsa_gen
> On 22.05.2020, at 16:13, Heiko Stuebner wrote:
>
> From: Heiko Stuebner
>
> Right now in multiple places there are only checks for the full
> CONFIG_RSA_VERIFY_WITH_PKEY option, not split into main,spl,tpl variants.
>
> This breaks when the rsa functions get enabled for SPL, for example t
Hi,
On Fri, 22 May 2020 at 00:18, Heinrich Schuchardt wrote:
>
> On 5/22/20 4:17 AM, Masahiro Yamada wrote:
> > On Fri, May 22, 2020 at 11:02 AM Simon Glass wrote:
> >>
> >> At present if an optional Kconfig value needs to be used it must be
> >> bracketed by #ifdef. For example, with this Kconf
> On 22.05.2020, at 16:13, Heiko Stuebner wrote:
>
> From: Heiko Stuebner
>
> padding_pss_verify only works with the default pss salt setting of -2
> (length to be automatically determined based on the PSS block structure)
> not -1 (salt length set to the maximum permissible value), which ma
Hi Alex,
On Thu, 21 May 2020 at 18:43, Alex Nemirovsky
wrote:
>
> From: Jway Lin
>
> Add Cortina Access LED controller support for CA SOCs
>
> Signed-off-by: Jway Lin
> Signed-off-by: Alex Nemirovsky
> CC: Simon Glass
>
> ---
>
> Changes in v8:
> - No code change
> - Split out individual
Hi Jagan,
On Thu, 14 May 2020 at 12:09, Jagan Teki wrote:
>
> Handling probing code for a particular uclass between
> dm vs nodm always confusing and requires additional
> ifdefs to handle them properly.
>
> But, having separate low-level code bases for dm and
> nodm can make it easy for the comm
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