This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.
The function has been tested pass on rk3399-evb and roc-rk3399-pc board.
For V5 update:
- Fix dwc3-generic driver followed Marek's comments for [PATCH v4 12/16].
- Add 'Reviewed-by' and 'Tested-by' tag for [PATCH v4 07
From: Jagan Teki
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-by: Jagan Teki
---
drivers/Makefile
From: Jagan Teki
Enable/Disable TCPHY clock for rk3399 platform.
Signed-off-by: Jagan Teki
---
drivers/clk/rockchip/clk_rk3399.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index 98fc6a3267
From: Jagan Teki
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
assigned-clocks = <&cru SC
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
Reviewed-by: Jagan Teki
Tested
From: Jagan Teki
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.
This will be reverted,
- Once we support the PHY subsystem to get the PHY
even though it
From: Jagan Teki
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.
When use this quirk, the controller implements a fixe
From: Jagan Teki
Add USB TYPEC PHY driver for rockchip platform.
Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
---
drivers/phy/rockchip/Kconfig | 7 +
drivers
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
drivers/usb/common/common.c | 25 ++
drivers/usb/dwc3/core.c |
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb-u-boot.d
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
---
drivers/usb/dwc3/dwc3
From: Jagan Teki
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).
Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with Retry
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
---
drivers/usb/host/Kconfig | 9 --
drivers/usb/host/Makefile| 1 -
drivers/usb/host/xhci-rockchip.
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.
Signed
Hi Jagan,
>-Original Message-
>From: Jagan Teki
>Sent: 13 May 2020 12:21
>To: Pragnesh Patel
>Cc: U-Boot-Denx ; Atish Patra
>; Palmer Dabbelt ; Bin
>Meng ; Paul Walmsley ;
>Anup Patel ; Sagar Kadam
>; Rick Chen ; Lukasz
>Majewski ; Anatolij Gustschin ; Simon
>Glass
>Subject: Re: [PATCH
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
---
configs/evb-rk3399_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 7f14e18b1b..6cfb4e5dac 100644
-
From: Jagan Teki
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki
---
drivers/clk/rockchip/clk_rk3399.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/c
From: Jagan Teki
Enable USB3.0 Host support for ROC-RK3399-PC boards.
Tested USB3.0 SSD on Type C1 port on board.
=> usb start
starting USB...
Bus usb@fe38: USB EHCI 1.00
Bus usb@fe3c: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controlle
On Wed, May 13, 2020 at 12:48 PM Pragnesh Patel
wrote:
>
> Hi Jagan,
>
> >-Original Message-
> >From: Jagan Teki
> >Sent: 13 May 2020 12:21
> >To: Pragnesh Patel
> >Cc: U-Boot-Denx ; Atish Patra
> >; Palmer Dabbelt ; Bin
> >Meng ; Paul Walmsley ;
> >Anup Patel ; Sagar Kadam
> >; Rick Che
>-Original Message-
>From: Jagan Teki
>Sent: 13 May 2020 13:30
>To: Pragnesh Patel
>Cc: U-Boot-Denx ; Atish Patra
>; Palmer Dabbelt ; Bin
>Meng ; Paul Walmsley ;
>Anup Patel ; Sagar Kadam
>; Rick Chen ; Lukasz
>Majewski ; Anatolij Gustschin ; Simon
>Glass
>Subject: Re: [PATCH v9 11/18] c
As discussed at
https://lore.kernel.org/linux-arm-kernel/b726290c-1038-3771-5187-6ac370bc9...@arm.com/T/
the defconfig for rpi4 miss CONFIG_ARCH_FIXUP_FDT_MEMORY.
Without it, booting with an initrd fail.
Signed-off-by: Corentin Labbe
---
Changes since v1:
- added fix for rpi_4_32b_defconfig
co
Hi David
On 5/12/20 11:56 AM, David Wu wrote:
> It seems dev_ functions are more general than fdt_ functions.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - None
>
> drivers/net/dwc_eth_qos.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/dw
On Wed, May 13, 2020 at 08:14:19AM +0200, Heinrich Schuchardt wrote:
> On 5/11/20 8:14 PM, Ilias Apalodimas wrote:
> > In OP-TEE we can run EDK2's StandAloneMM on a secure partition.
> > StandAloneMM is responsible for the UEFI variable support. In
> > +
[...]
> > + EFI_ENTRY("%p \"%ls\" %pUl",
Hi David
On 5/12/20 11:56 AM, David Wu wrote:
> It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
> gpio is used, adding this option makes reset function more general.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - Remove the code is not related (Patrice)
>
> driver
On 5/12/20 11:56 AM, David Wu wrote:
> After moving to eqos_ops, if eqos_config is defined
> outside file, can not export interface() definition,
> only export eqos_ops struct defined in dwc_eth_qos.c.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - None
>
> drivers/net/dwc_eth_qos.c |
Hi David
On 5/12/20 11:56 AM, David Wu wrote:
> For others using, clk_rx and clk_tx may not be necessary,
> and their clock names are different.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - Don't change the Rx and Tx clock names. (Patrice, Stephen)
>
> drivers/net/dwc_eth_qos.c | 61
one typo below
On 5/12/20 11:57 AM, David Wu wrote:
> For Rockchip, need to obtain the current link speed to
> configure the tx clocks, (for example, in rgmii mode,
> 1000M link: 125M, 100M link: 25M, 10M link is 2.5M rate)
> and then enable gmac. So after the adjust_link(), before
> the start gam
Hi David
On 5/12/20 11:57 AM, David Wu wrote:
> If there are definitions for eqos_start_clks and eqos_stop_clks,
> then call these callback function.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - None
>
> drivers/net/dwc_eth_qos.c | 16 ++--
> 1 file changed, 10 insertions(
Hi David
On 5/12/20 11:57 AM, David Wu wrote:
> Open structure data and interface, so that Soc using dw_eth_qos
> controller can reference.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - Add the lost head file. (Patrice)
>
> drivers/net/dwc_eth_qos.c | 81 --
Hi David
On 5/12/20 11:58 AM, David Wu wrote:
> The Rockchip CSR clock range is from 100M to 150M, add
> EQOS_MAC_MDIO_ADDRESS_CR_100_150.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - None
>
> drivers/net/dwc_eth_qos.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
HI David
On 5/12/20 11:58 AM, David Wu wrote:
> The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
Typo simillar
> export the eqos_rockchip_ops to use.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - None
>
> drivers/net/dwc_eth_qos.c | 16
> drivers/net/dwc_et
On 13/05/20 12:17PM, Jagan Teki wrote:
> On Mon, Mar 30, 2020 at 9:16 PM Pratyush Yadav wrote:
> >
> > When the flash is handed to us in a stateful mode like 8D-8D-8D, it is
> > difficult to detect the mode the flash is in. One option is to read SFDP
> > in all modes and see which one gives the co
On 11/05/2020 15:17, Neil Armstrong via groups.io wrote:
> Enable options to permit HDMI output on Khadas VIM3 & VIM3L boards.
>
> Signed-off-by: Neil Armstrong
> ---
> configs/khadas-vim3_defconfig | 9 +
> configs/khadas-vim3l_defconfig | 4
> 2 files changed, 13 insertions(+)
>
On 11/05/2020 15:17, Neil Armstrong wrote:
> Include the common g12 u-boot tweaks to permit enabling video output tweaks
> on Khadas VIM3 boards.
>
> Signed-off-by: Neil Armstrong
> ---
> arch/arm/dts/meson-khadas-vim3-u-boot.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/
Dear Marek,
> From: Marek Vasut
> Sent: mardi 12 mai 2020 19:07
>
> Make the bsec driver available both in SPL and in U-Boot proper to make it
> possible to read out the SoC type (A/C/D/F) and thus to determine the MPU PLL
> configuration (650/800 MHz).
>
> Signed-off-by: Marek Vasut
> Cc: Pa
On 13.05.20 08:26, Pragnesh Patel wrote:
> When build U-Boot SPL, meet an issue of undefined reference to
> 'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
> CONFIG_MMC_SPI selected.
>
> Signed-off-by: Pragnesh Patel
Reviewed-by: Heinrich Schuchardt
> ---
> lib/Makefile | 2 +-
>
Dear Marek,
> From: Marek Vasut
> Sent: mardi 12 mai 2020 19:07
>
> There are two speed grades of the STM32MP1, the A/C and D/F, the former can
> run up to 650 MHz, the later at up to 800 MHz. Allow specifying PLL config for
> both in the DT, so that it is possible to cater for boards which can
> Date: Tue, 28 Apr 2020 20:26:09 +0200
> From: Lukasz Majewski
Ping?
> Hi Mark,
>
> > > Date: Tue, 28 Apr 2020 06:24:10 +0200
> > > From: Lukasz Majewski
> >
> > Hi Lukasz,
> >
> > > Hi Mark,
> > >
> > > > The fix in commit b7adcdd073c0 has the side-effect that the
> > > > regulator wi
On 12.05.2020 20:47, Sylwester Nawrocki wrote:
> This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
> and USB commands. To get it working one has to call the following commands:
> "pci enum; usb start;", thus such commands have been added to the default
> "preboot" environment
Dear Marek,
> From: Marek Vasut
> Sent: mercredi 29 avril 2020 15:09
>
> Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put
> them into use by the board file instead of the default ones. These new DRAM
> settings are a better fit for the SoMs.
>
> Signed-off-by: Marek Vasut
> Cc
On Tue, May 12, 2020 at 05:22:38PM -0600, Simon Glass wrote:
> Hi Andy,
>
> On Tue, 12 May 2020 at 06:32, Andy Shevchenko
> wrote:
> >
> > On Tue, May 12, 2020 at 01:55:49PM +0200, Wolfgang Wallner wrote:
> >
> > > > Since you were involved a lot in the discussion in the part A series,
> > > > wo
On Wed, May 13, 2020 at 2:24 PM Pratyush Yadav wrote:
>
> On 13/05/20 12:17PM, Jagan Teki wrote:
> > On Mon, Mar 30, 2020 at 9:16 PM Pratyush Yadav wrote:
> > >
> > > When the flash is handed to us in a stateful mode like 8D-8D-8D, it is
> > > difficult to detect the mode the flash is in. One opt
Hi Stephen and Marek
> From: Stephen Warren
> Sent: mercredi 29 avril 2020 23:51
> To: Marek Vasut
> Cc: u-boot@lists.denx.de; Joe Hershberger ; Patrice
> CHOTARD ; Patrick DELAUNAY
> ; Ramon Fried ; Stephen
> Warren ; Tom Warren
> Subject: Re: [PATCH] net: dwc_eth_qos: Pad descriptors to cache
On 13/05/2020 10:07, Corentin Labbe wrote:
> As discussed at
> https://lore.kernel.org/linux-arm-kernel/b726290c-1038-3771-5187-6ac370bc9...@arm.com/T/
> the defconfig for rpi4 miss CONFIG_ARCH_FIXUP_FDT_MEMORY.
> Without it, booting with an initrd fail.
>
> Signed-off-by: Corentin Labbe
> --
On 13/05/20 03:26PM, Jagan Teki wrote:
> On Wed, May 13, 2020 at 2:24 PM Pratyush Yadav wrote:
> >
> > On 13/05/20 12:17PM, Jagan Teki wrote:
> > > On Mon, Mar 30, 2020 at 9:16 PM Pratyush Yadav wrote:
> > > >
> > > > When the flash is handed to us in a stateful mode like 8D-8D-8D, it is
> > > >
From: Jan Luebbe
If "object=" is specified in "keydir" when using the pkcs11 engine do
not append another "object=". This makes it possible to
use object names other than the key name hint. These two string
identifiers are not necessarily equal.
Signed-off-by: Jan Luebbe
Signed-off-by: Bastian
On 5/13/20 2:47 AM, Frank Wang wrote:
> Hi Marek,
>
> On 2020/5/12 15:26, Marek Vasut wrote:
>> On 5/12/20 3:08 AM, Frank Wang wrote:
>>> Hi Marek,
>>>
>>> On 2020/5/11 17:48, Marek Vasut wrote:
On 5/11/20 9:57 AM, Frank Wang wrote:
[...]
> @@ -394,6 +407,12 @@ static int dwc3_g
On 5/13/20 11:12 AM, Patrick DELAUNAY wrote:
> Dear Marek,
>
>> From: Marek Vasut
>> Sent: mardi 12 mai 2020 19:07
>>
>> There are two speed grades of the STM32MP1, the A/C and D/F, the former can
>> run up to 650 MHz, the later at up to 800 MHz. Allow specifying PLL config
>> for
>> both in the
On Wed, May 13, 2020 at 12:38:58PM +0200, Matthias Brugger wrote:
>
>
> On 13/05/2020 10:07, Corentin Labbe wrote:
> > As discussed at
> > https://lore.kernel.org/linux-arm-kernel/b726290c-1038-3771-5187-6ac370bc9...@arm.com/T/
> > the defconfig for rpi4 miss CONFIG_ARCH_FIXUP_FDT_MEMORY.
> > Wi
On 12/05/2020 12:02, matthias@kernel.org wrote:
> From: Matthias Brugger
>
> If CONFIG_MMC_SDHCI_SDMA is enabled but the HW could not support it,
> we no longer error out. Instead we do not enable it in the host.
> Change the output from printf to debug as this isn't an error but only
> ad
On 12/05/2020 12:02, matthias@kernel.org wrote:
> From: Matthias Brugger
>
> RPi4 supports SDMA on it's SDHCI controller. Enable to option for
> the combine RPi3/4 config.
>
> Signed-off-by: Matthias Brugger
>
> ---
Queued for rpi-next
>
> configs/rpi_arm64_defconfig | 1 +
> 1 file
Hi Patrice
> From: Patrice CHOTARD
> Sent: jeudi 30 avril 2020 18:41
>
> On DK1/2 board, when a 1.5A power supply is detected, a warning message is
> displayed. In this message, "1.5mA" is displayed instead of "1.5A".
>
> Signed-off-by: Patrice Chotard
> ---
>
> board/st/stm32mp1/stm32mp1.c
On 26/02/2020 22:37, kev...@freebsd.org wrote:
> From: Kyle Evans
>
> While the nearly-universal default for the Raspberry Pi family is to use
> spin tables and the spin table implementation provided by the Raspberry Pi
> Foundation, FreeBSD and others may use a PSCI implementation instead.
>
On 26/02/2020 22:39, kev...@freebsd.org wrote:
> From: Kyle Evans
>
> Some systems may use a slightly larger stub to do PSCI for booting the RPi
> family. The number of pages has been made configurable so that operating
> systems building U-Boot for use in these kinds of environments can rese
Hi Simon,
-"Simon Glass" schrieb: -
>Betreff: [PATCH v2 03/35] acpi: Add a way to check device status
>
>At present U-Boot does not support the different ACPI status values,
>but
>it is best to put this logic in a central place. Add a function to
>get the
>device status.
>
>Signed-off-by:
Hi Marek,
> From: Marek Vasut
> Sent: mercredi 13 mai 2020 12:53
>
> On 5/13/20 11:12 AM, Patrick DELAUNAY wrote:
> > Dear Marek,
> >
> >> From: Marek Vasut
> >> Sent: mardi 12 mai 2020 19:07
> >>
> >> There are two speed grades of the STM32MP1, the A/C and D/F, the
> >> former can run up to 65
This patch-series enables u-boot to be booted from SPI-NAND
memory on sunxi SoCs. Development was done and tested on a sun8i V3s.
To accomplish this, the changes where split in 4 different
patches. The following list describes the patches, their
title, their message ID and contain their commit-me
Hi Marek,
> From: Marek Vasut
> Sent: mardi 12 mai 2020 18:58
>
> On 4/29/20 3:08 PM, Marek Vasut wrote:
> > Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put
> them
> > into use by the board file instead of the default ones. These new DRAM
> > settings are a better fit for the S
On 5/13/20 2:26 PM, Patrick DELAUNAY wrote:
> Hi Marek,
>
>> From: Marek Vasut
>> Sent: mardi 12 mai 2020 18:58
>>
>> On 4/29/20 3:08 PM, Marek Vasut wrote:
>>> Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put
>> them
>>> into use by the board file instead of the default ones. Th
On 5/13/20 2:23 PM, Patrick DELAUNAY wrote:
> Hi Marek,
>
>> From: Marek Vasut
>> Sent: mercredi 13 mai 2020 12:53
>>
>> On 5/13/20 11:12 AM, Patrick DELAUNAY wrote:
>>> Dear Marek,
>>>
From: Marek Vasut
Sent: mardi 12 mai 2020 19:07
There are two speed grades of the STM32MP1
I decided to check out USB gadget ethernet in u-boot and selected
USB_ETHER/USB_ETH_RNDIS and tried
to build it but that fails due to missing __constant_cpu_to_leXX() definitions.
These are nowhere to find in u-boot so I wonder what shape above code is?
Jocke
sorry for the delay ;)
Am 02.05.20 um 10:59 schrieb Stefan Roese:
> From: Aaron Williams
>
> This patch adds very basic support for the Octeon III SoCs. Only
> CFI parallel NOR flash and UART is supported for now.
>
> Please note that the basic Octeon port does not include the DDR3/4
> initiali
Hi David
> From: David Wu
> Sent: mardi 12 mai 2020 11:56
>
> It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
> gpio is used, adding this option makes reset function more general.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - Remove the code is not related (Pa
Hi All,
I am trying to use 'cpu' command, so I modified config file and compiled
u-boot with a 'cpu' command enabled. But when I try to use it properly
it's completely silent.
It appeared that this behaviour is caused by list at 'dev_head' always
being empty in the corresponding uclass.
But d
On Tue, 2020-05-05 at 18:26 +0200, Nicolas Saenz Julienne wrote:
> Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be
> loaded explicitly. Earlier versions didn't need that as they where using
> an EEPROM for that purpose. This series takes care of setting up the
> relevant inf
Dear David,
> From: David Wu
> Sent: mardi 12 mai 2020 11:56
>
> It seems dev_ functions are more general than fdt_ functions.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - None
>
> drivers/net/dwc_eth_qos.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff
Am 02.05.20 um 10:59 schrieb Stefan Roese:
> This patch enables the usage of CONFIG_MIPS_L2_CACHE without
> CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
> platform.
>
> Signed-off-by: Stefan Roese
> ---
>
> arch/mips/lib/cache.c | 13 -
> 1 file changed, 12
On 5/13/20 2:58 PM, Patrick DELAUNAY wrote:
> Dear David,
>
>> From: David Wu
>> Sent: mardi 12 mai 2020 11:56
>>
>> It seems dev_ functions are more general than fdt_ functions.
>>
>> Signed-off-by: David Wu
It seems Joe still didn't come back, I have patches open for two+ months
now. What do
Hi Simon,
-"Simon Glass" schrieb: -
>Betreff: [PATCH v2 04/35] irq: Add a method to convert an interrupt
>to ACPI
>
>When generating ACPI tables we need to convert IRQs in U-Boot to the
>ACPI
>structures required by ACPI. This is a SoC-specific conversion and
>cannot
>be handled by generi
On Wed, May 13, 2020 at 5:26 AM Bastian Krause wrote:
>
> From: Jan Luebbe
>
> If "object=" is specified in "keydir" when using the pkcs11 engine do
> not append another "object=". This makes it possible to
> use object names other than the key name hint. These two string
> identifiers are not ne
Am 02.05.20 um 10:59 schrieb Stefan Roese:
> The Octeon platform is cache coherent and cache flushes and invalidates
> are not needed. This patch makes use of the newly introduced Kconfig
> option CONFIG_MIPS_CACHE_COHERENT to effectively disable all the cache
> operations.
I don't like this ex
Am 02.05.20 um 10:59 schrieb Stefan Roese:
> WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
> the exception base register.
>
> Signed-off-by: Stefan Roese
> ---
>
> arch/mips/lib/traps.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/mips/lib/traps.
Am 02.05.20 um 10:59 schrieb Stefan Roese:
> With the introduction of the MIPS Octeon support, lets use the newly
> added Kconfig symbol CONFIG_CPU_MIPS64_OCTEON instead of the old Linux
> CONFIG_CPU_CAVIUM_OCTEON one (which was never set). Remove these
> references completely with this patch.
Hi David,
> From: David Wu
> Sent: mardi 12 mai 2020 11:56
>
> For others using, clk_rx and clk_tx may not be necessary, and their clock
> names
> are different.
>
> Signed-off-by: David Wu
> ---
>
> Changes in v2:
> - Don't change the Rx and Tx clock names. (Patrice, Stephen)
>
> drivers/
On 5/13/20 3:17 PM, Patrick DELAUNAY wrote:
> Hi David,
>
>> From: David Wu
>> Sent: mardi 12 mai 2020 11:56
>>
>> For others using, clk_rx and clk_tx may not be necessary, and their clock
>> names
>> are different.
>>
>> Signed-off-by: David Wu
>> ---
>>
>> Changes in v2:
>> - Don't change the
Hi Eugeniy,
> -Original Message-
> From: Eugeniy Paltsev
> Sent: Saturday, April 25, 2020 12:11 AM
> To: Alexey Brodkin
> Cc: u-boot@lists.denx.de; uboot-snps-...@synopsys.com; Eugeniy Paltsev
>
> Subject: [PATCH] BDINFO: ARC: print info about relocations
>
> Print relocation informat
When not booting from FlexSPI, the offset computation is:
offset = image_offset + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000;
When booting from SD card or eMMC user partition, image_offset is
0x8000. It is useless to add and remove 0x8000.
When booting from other device, image_offset
This code is very old and has not had much of a clean-up since it was
written. This series aims to tidy it up to use error codes, avoid using
BSS when not necessary and to add a few more features.
Simon Glass (13):
cbfs: Rename the result variable
cbfs: Use ulong consistently
cbfs: Use bool
At present the result variable in the cbfs_priv is called 'result' as is
the local variable in a few functions. Change the latter to 'ret' which is
more common in U-Boot and avoids confusion.
Signed-off-by: Simon Glass
---
fs/cbfs/cbfs.c | 20 ++--
1 file changed, 10 insertions(
U-Boot uses ulong for addresses but there are a few places in this driver
that don't use it. Convert this driver over to follow this convention
fully.
Signed-off-by: Simon Glass
---
fs/cbfs/cbfs.c | 9 -
include/cbfs.h | 4 ++--
2 files changed, 6 insertions(+), 7 deletions(-)
diff --g
At present this uses an int type. U-Boot now supports bool so use this
instead. Also use English spelling for initialised which we are here.
Signed-off-by: Simon Glass
---
fs/cbfs/cbfs.c | 28 ++--
include/cbfs.h | 2 +-
2 files changed, 15 insertions(+), 15 deletions(-
These two functions have mostly the same code. Pull this out into a common
function.
Also make this function zero the private data so that callers don't have
to do it. Finally, update cbfs_load_header_ptr() to take the base of the
ROM as its parameter, which makes more sense than passing the addre
This function is strange at the moment in that it takes a header pointer
but then accesses the cbfs_s global. Currently clients have their own priv
pointer, so update the function to take that as a parameter instead.
Signed-off-by: Simon Glass
---
fs/cbfs/cbfs.c | 9 +
1 file changed, 5
This function is strange at the moment in that it takes a header pointer
but then accesses the cbfs_s global. Currently clients have their own priv
pointer, so update the function to take that as a parameter instead.
Signed-off-by: Simon Glass
---
fs/cbfs/cbfs.c | 9 ++---
1 file changed, 6
At present his uses a true return to indicate it found a file. Adjust it
to use 0 for this, so it is consistent with other functions.
Update its callers accordingling and add a check for malloc() failure in
file_cbfs_fill_cache().
Signed-off-by: Simon Glass
---
fs/cbfs/cbfs.c | 43
The start address of the CBFS is used when scanning for files. It makes
sense to put this in our cbfs_priv struct and calculate it when we read
the header.
Update the code accordingly.
Signed-off-by: Simon Glass
---
fs/cbfs/cbfs.c | 44 +++-
1 file chang
This function currently returns a node pointer so there is no way to know
the error code. Also it uses data in BSS which seems unnecessary since the
caller might prefer to use a local variable.
Update the function and split its body out into a separate function so we
can use it later.
Signed-off-
The size is not actually used since it is present in the header. Drop this
parameter. Also tidy up error handling while we are here.
Signed-off-by: Simon Glass
---
arch/x86/lib/fsp2/fsp_init.c | 3 +--
fs/cbfs/cbfs.c | 9 +
include/cbfs.h | 3 +--
3 files cha
It doesn't make sense to use u8 * as the pointer type for accessing the
CBFS since we do not access it as bytes, but via structures. Change it to
void *, which allows us to avoid a cast.
Signed-off-by: Simon Glass
---
fs/cbfs/cbfs.c | 17 -
1 file changed, 8 insertions(+), 9 del
We may as well return the error code and use it directly in the command
code. CBFS still uses its own error enum which we may be able to remove,
but leave it for now.
Signed-off-by: Simon Glass
---
cmd/cbfs.c | 3 +--
fs/cbfs/cbfs.c | 23 +++
include/cbfs.h | 6 +++---
Currently we support reading a file from CBFS given the address of the end
of the ROM. Sometimes we only know the start of the CBFS. Add a function
to find a file given that.
Signed-off-by: Simon Glass
---
fs/cbfs/cbfs.c | 13 +
include/cbfs.h | 11 +++
2 files changed, 24 i
On Tue, May 12, 2020 at 11:04:38PM -0400, Tom Rini wrote:
> On Mon, May 11, 2020 at 09:08:03PM +0200, Heinrich Schuchardt wrote:
> > On 5/11/20 8:40 PM, Tom Rini wrote:
> > > On Sun, May 10, 2020 at 10:12:07PM +0900, Masahiro Yamada wrote:
> > >> On Sun, May 10, 2020 at 12:12 AM Heinrich Schuchardt
Am 02.05.20 um 10:59 schrieb Stefan Roese:
> This patch adds very basic minimal support for the Marvell Octeon 3
> CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
> not support DDR3/4 initialization yet. To still use U-Boot on with this
> port, the L2 cache (4MiB) is used a
On Wed, May 13, 2020 at 08:13:45AM +0200, Heiko Schocher wrote:
> Hello Heinrich,
>
> Am 13.05.2020 um 07:53 schrieb Heinrich Schuchardt:
> > On 5/13/20 5:54 AM, Heiko Schocher wrote:
> > > Hello Tom,
> > >
> > > Am 12.05.2020 um 15:28 schrieb Heiko Schocher:
> > > > Hello Tom,
> > > >
> > > > A
On 5/13/20 4:49 PM, Tom Rini wrote:
> On Wed, May 13, 2020 at 08:13:45AM +0200, Heiko Schocher wrote:
>> Hello Heinrich,
>>
>> Am 13.05.2020 um 07:53 schrieb Heinrich Schuchardt:
>>> On 5/13/20 5:54 AM, Heiko Schocher wrote:
Hello Tom,
Am 12.05.2020 um 15:28 schrieb Heiko Schocher:
>
On Wed, May 13, 2020 at 04:52:26PM +0200, Marek Vasut wrote:
> On 5/13/20 4:49 PM, Tom Rini wrote:
> > On Wed, May 13, 2020 at 08:13:45AM +0200, Heiko Schocher wrote:
> >> Hello Heinrich,
> >>
> >> Am 13.05.2020 um 07:53 schrieb Heinrich Schuchardt:
> >>> On 5/13/20 5:54 AM, Heiko Schocher wrote:
>
Am 02.05.20 um 10:59 schrieb Stefan Roese:
> This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
> family.
>
> Signed-off-by: Stefan Roese
> ---
>
> drivers/sysreset/Kconfig | 7
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_octeon.
From: Corneliu Doban
Add eMMC and GPT support.
- GPT partition list and command to create the GPT added to u-boot
environment
- eMMC boot commands added to u-boot environment
- new gpt commands (enumarate and setenv) that are used by broadcom
update scripts and boot commands
- eMMC specific u
Hi Tom,
The following changes since commit 10bca13ea6d9d4b85f80f02c8795227f63240f59:
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb (2020-05-12
16:20:10 -0400)
are available in the Git repository at:
g...@gitlab.denx.de:u-boot/custodians/u-boot-arc.git
tags/arc-fixes-for-2020.0
This change updates the MTD partition layout on SPI-NOR memory for display5
board.
Signed-off-by: Lukasz Majewski
---
configs/display5_defconfig | 2 +-
configs/display5_factory_defconfig | 2 +-
include/configs/display5.h | 7 ---
3 files changed, 6 insertions(+), 5 deletio
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