Have tested this Patch, fixes the binman-issue on bpi-r2/bpi-r64
Tested-by: Frank Wunderlich
@tom can you merge this until next rc?
regards Frank
From: Eugeniu Rosca
Replace 'u32' by 'uint32_t' in image.h, since the former may lead to
build failures in U-Boot tooling (see [1]).
Avoid using 'uint', since it is not a fixed-width type [2], potentially
leading to a dangerous mismatch between the prototypes and definitions
of the android_image
Hello Heinrich,
Thank you for your perseverance.
I was just about to reply in https://patchwork.ozlabs.org/patch/1239098.
On Sat, Mar 07, 2020 at 10:53:44AM +0100, Heinrich Schuchardt wrote:
> From: Eugeniu Rosca
>
> Replace 'u32' by 'uint32_t' in image.h, since the former may lead to
> build f
Hi,
On 07/03/2020 06:42, Amit Singh Tomar wrote:
> This patch converts S900 clock driver to something common that can
> be used for other SoCs, for instance S700(few of clk registers are same).
>
> Signed-off-by: Amit Singh Tomar
> ---
> Changes since v3:
> * Fixed register spelling.
>
Hi,
> Both those include files do not exist yet. This breaks bisectability for
> bubblegum_96.
> So I would suggest you remove the s700 lines for now, and change the
> s900 filename to match the existing one.
> Then change CLK_UART to CLOCK_UART below to make it compile.
>
> Please check that bubb
From: Hiroyuki Yokoyama
In R-Car Gen 3, there is a DMA controller restriction of SDHI.
When the transfer exceeding the 4 kByte boundary is performed while
the DRAM address is not 128 byte aligned, the bus is occupied.
This patch avoids this.
Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek
Add extended version of the bounce_buffer_start(), which permits passing in
a custom alignment checker function for the buffer. This is useful e.g. on
systems with various DMA restrictions and where the checker function might
be more complex than a simple CPU cache alignment check.
Signed-off-by:
The R-Car SDHI DMA controller has various restrictions. To work around
those restrictions without falling back to PIO, implement bounce buffer
with custom alignment check function which tests for those limitations.
Signed-off-by: Marek Vasut
Cc: Daniel Schwierzeck
Cc: Masahiro Yamada
Cc: Peng F
Increase the malloc area size significantly to cater for bounce buffer
used by the SDHI driver.
Signed-off-by: Marek Vasut
Cc: Daniel Schwierzeck
Cc: Masahiro Yamada
Cc: Peng Fan
Cc: Simon Glass
Cc: Tom Rini
---
include/configs/rcar-gen3-common.h | 2 +-
1 file changed, 1 insertion(+), 1 de
Add getter function which permits adjusting the maximum number of
blocks that could be read in a single sustained read transfer based
on the location of the source/target buffer and length, before such
transfer starts.
This is mainly useful on systems which have various DMA restrictions
for differ
Implement get_b_max() for the Renesas R-Car SDHI controller driver, limit
the b_max per hardware capabilities such that select Gen2 controllers have
16bit block transfer limit, the rest has 32bit block transfer limit and on
Gen3, the block transfer limit on addresses above the 32bit boundary is set
On 07/03/2020 15:30, Amit Tomer wrote:
> Hi,
>
>> Both those include files do not exist yet. This breaks bisectability for
>> bubblegum_96.
>> So I would suggest you remove the s700 lines for now, and change the
>> s900 filename to match the existing one.
>> Then change CLK_UART to CLOCK_UART belo
On 3/7/20 1:52 PM, Eugeniu Rosca wrote:
Hello Heinrich,
Thank you for your perseverance.
I was just about to reply in https://patchwork.ozlabs.org/patch/1239098.
On Sat, Mar 07, 2020 at 10:53:44AM +0100, Heinrich Schuchardt wrote:
From: Eugeniu Rosca
Replace 'u32' by 'uint32_t' in image.h, s
It is useful to be able to boot the same x86 image on a device with or
without a first-stage bootloader. For example, with chromebook_coral, it
is helpful for testing to be able to boot the same U-Boot (complete with
FSP) on bare metal and from coreboot. It allows checking of things like
CPU speed,
This little series adds a few checks into the code to allow better
operation when booting a build from a previous-state loader such as
coreboot.
At present we have a 'coreboot' target but this runs very different code
from the bare-metal targets, such as coral. There is very little in common
betwe
When U-Boot is not the first-stage bootloader the interrupt and cache init
must be skipped, as well as init for various peripherals. Update the code
to add checks for this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Drop the other check in interrupt_init() which is not n
With chromebook_coral we normally run TPL->SPL->U-Boot. This is the
'bare metal' case.
When running from coreboot we put u-boot.bin in the RW_LEGACY portion
of the image, e.g. with:
cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \
-f /tmp/b/chromebook_coral/u-boot.bin -n
When U-Boot is run from another boot loader, much of the low-level init
needs to be skipped.
Add a flag for this and adjust ll_boot_init() to use it.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add a new patch with a gd flag for chain loading
Changes in v2: None
include/asm-generic/globa
When U-Boot is not the first-stage bootloader the FSP-S init must be
skipped. Update it to add a check.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b
If U-Boot is running from coreboot we need to skip low-level init. Add
an way to detect this and to set the gd flag.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch to detect running from coreboot
Changes in v2: None
arch/x86/cpu/i386/cpu.c | 15 +++
arch/x
When U-Boot is not the first-stage bootloader we don't want to
re-configure the PCI devices, since this has already been done. Add a
check to avoid this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Drop patch 'dm: Avoid initing built-in devices when chain loading'
drive
On Feb. 16, 2020, Tom reported [1] build failure of U-Boot in-tree
tooling after applying https://patchwork.ozlabs.org/cover/1229663/
("[v6,0/7] rsa: extend rsa_verify() for UEFI secure boot").
Later on, Heinrich stressed the urgency of the issue in
https://patchwork.ozlabs.org/patch/1250858/#2379
Hello Heinrich,
On Sat, Mar 07, 2020 at 09:31:17PM +0100, Heinrich Schuchardt wrote:
> Whichever way you want to go we should finalize the topic as it stops
> EFI patches from being merged.
Could you please review https://patchwork.ozlabs.org/patch/1250963/ ?
--
Best Regards
Eugeniu Rosca
Hi Walter,
Thanks for your SPL_DM support work on this platform.
One comment inline below.
On Wed, Mar 04 2020, Walter Lozano wrote:
> MMC iomux is done on board_mmc_init which is valid when DM_MMC is not
> enabled. After enabling it, the iomux setup needs to be moved to a
> valid place.
>
> Thi
Hi Walter,
On Wed, Mar 04 2020, Walter Lozano wrote:
> In SPL legacy code only one MMC device is created, based on BOOT_CFG
> register, which can be either SD or eMMC. In this context
> board_boot_order return always MMC1 when configure to boot from
> SD/eMMC. After switching to DM both SD and eMM
Hi,
>-Original Message-
>From: Palmer Dabbelt
>Sent: 06 March 2020 22:32
>To: Pragnesh Patel
>Cc: u-boot@lists.denx.de; Atish Patra ;
>bmeng...@gmail.com; Paul Walmsley ;
>ja...@amarulasolutions.com; Troy Benjegerdes
>; Anup Patel ; Sagar
>Kadam ; Pragnesh Patel
>
>Subject: Re: [PATCH v4
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