On Mon, Nov 25, 2019 at 12:11 PM Simon Glass wrote:
>
> Add a simple sandbox test for this uclass.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v5: None
> Changes in v4:
> - Drop itss uclass change in Makefile (now in previous patch)
> - Drop sandbox defconfig change now that p2sb change i
On Mon, Nov 25, 2019 at 12:11 PM Simon Glass wrote:
>
> This should take account of the end of the new cache record since a record
> cannot extend beyond the end of the flash region. This problem was not
> seen before due to the alignment of the relatively small amount of MRC
> data.
>
> But with
On Mon, Nov 25, 2019 at 12:11 PM Simon Glass wrote:
>
> Change the algorithm to first find the flash device then read the
> properties using the livetree API. With this change the device is not
> probed so this needs to be done in mrccache_save().
>
> Signed-off-by: Simon Glass
> ---
>
> Changes
On Mon, Nov 25, 2019 at 12:11 PM Simon Glass wrote:
>
> This function is only used within the implementation so make it static.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v5: None
> Changes in v4:
> - Add new patch to make mrccache_update() static
>
> Changes in v3: None
> Changes in v2:
On Mon, Nov 25, 2019 at 12:11 PM Simon Glass wrote:
>
> It is now possible to obtain the memory map for a SPI controllers instead
> of having it hard-coded in the device tree. Update the code to support
> this.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v5: None
> Changes in v4: None
> C
Hi All!
This patchset enables support for DFU over USB protocol on Raspberry Pi4
board. The board has DWC2 UDC controller connected to the USB-C power
connector. Enabling DFU on it, make the u-boot development much more
convenient, as one no longer needs to swap SD-card between RPi4 board and
host
The code for handing file overwrite incorrectly assumed that the file on
disk is always contiguous. This resulted in corrupting disk structure
every time when write to existing fragmented file happened. Fix this
by adding proper check for cluster discontinuity and adjust chunk size
on each partial
Rename functions for bufferred file io operations to make them easier to
understand. Also add missing file offset argument to them (currently
unused). All this is a preparation to remove predefined file size limit
(CONFIG_SYS_DFU_MAX_FILE_SIZE) for DFU read/write operations.
Signed-off-by: Marek S
Add support for operations on files larger than
CONFIG_SYS_DFU_MAX_FILE_SIZE. The buffered io mechanism is still used for
aggregating io requests, so for files up to CONFIG_SYS_DFU_MAX_FILE_SIZE
nothing is changed and they will be handled in a single filesystem call.
Signed-off-by: Marek Szyprowsk
Broadcom 2835 SoC requires special conversion of physical memory addresses
for DMA purpose, so add needed wrappers to dwc2_udc_otg driver. Also extend
the list of compatible devices with 'brcm,bcm2835-usb' entry. This allows
to use USB gadget drivers (i.e. DFU) on Raspberry Pi4 boards.
Signed-off-
Handling of the start file offset was broken in the current code. Although
the code skipped the needed clusters, it then tried to continue write with
current cluster set to EOF, what caused assertion. It also lacked adjusting
filesize in case of writing at the end of file and adjusting in-cluster
o
Enable support for DFU over USB. This requires to enable USB gadget,
DWC2 UDC OTG driver and DFU command. DFU entities are defined for the
following firmware objects: u-boot.bin, uboot.env, config.txt, and
zImage/Image.
Signed-off-by: Marek Szyprowski
Reviewed-by: Lukasz Majewski
---
configs/rp
Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3,
ship with the controller default address.
Add a config option to fix it up so it can function properly.
Signed-off-by: Andre Heider
---
arch/arm/mach-sunxi/Kconfig | 12
board/sunxi/board.c | 30
That helper takes care of assembling the correct name and doesn't allow
overwriting existing env vars, so drop the checks here.
Signed-off-by: Andre Heider
---
board/sunxi/board.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/boar
Changes since v1:
* add CONFIG_FIXUP_BDADDR so fixing up a bdaddr is reusable
* try to use "bdaddr" first, then fall back to generating an address
Notes:
* the kernel patch for btbcm to accept the "local-bd-address"
property just hit mainline.
Andre Heider (4):
sunxi: board: Use eth_env_set_e
The dts is taken from kernel tag v5.4.
The Bluetooth controller of this device ships with a default adress,
use the new CONFIG_FIXUP_BDADDR option to fix it up.
Signed-off-by: Andre Heider
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun50i-h6-orangepi-3.dts | 287 +++
Taken from the kernel tag v5.4.
Drop the /omit-if-no-ref/ keyword as it's not supported by u-boot.
Signed-off-by: Andre Heider
---
arch/arm/dts/sun50i-h6-beelink-gs1.dts | 27 +
arch/arm/dts/sun50i-h6-orangepi.dtsi | 4 +
arch/arm/dts/sun50i-h6-pine-h64.dts| 4 +
arch/arm/dts/sun5
On 11/26/19 3:47 AM, Masahiro Yamada wrote:
> On Thu, Nov 21, 2019 at 6:38 AM Marek Vasut wrote:
>>
>> Legacy kernel versions for SoCFPGA may not implement proper reset
>> handling.
>
> What is "legacy kernel versions" ?
Anything older than 5.x , which got proper reset handling, finally.
>> Appl
On 11/26/19 12:16 AM, Heinrich Schuchardt wrote:
> Dear maintainers,
Hi,
> we have been trying to move to the driver model for several years now.
> Starting in 2018 we have added warnings to the Makefile that boards not
> supporting the driver model will be eliminated. Still 24 % of the
> configu
On 20/11/19 11:33:10, Jens Wiklander wrote:
> On Wed, Nov 20, 2019 at 09:21:35AM +0100, Jorge Ramirez-Ortiz wrote:
> > On 11/20/19 8:20 AM, Jens Wiklander wrote:
> > > On Tue, Nov 19, 2019 at 06:21:34PM +0100, Jorge Ramirez-Ortiz wrote:
> > >> On 11/19/19 12:53 PM, Jorge Ramirez-Ortiz wrote:
> > >>
Move Stratix10 and Agilex reset manager common code to
reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*.
Remove unused RSTMGR_XXX defines.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v5:
- Remove reset_manager_s10.h and use reset_manager_soc64.h directly.
v4:
- Chang
On 11/26/19 3:34 AM, Masahiro Yamada wrote:
> On Thu, Nov 21, 2019 at 6:37 AM Marek Vasut wrote:
>>
>> While the Denali NAND is initialized by the BootROM in SPL, there
>> are still a couple of settings which are missing. These can trigger
>> subtle corruption of the data read out of the NAND. Fill
Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 9 +++--
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 5 +++--
2 files changed, 10 insertions(+)
This is 7th version of patchset to add Intel Agilex SoC[1] support.
This patchset needs to apply after patchset in [2] for manager driver
struct to defines conversion and [3] for enable cache driver build in SPL.
Patch status:
Have changes: Patch 17, 19
Other patches unchanged.
Detail changelog
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v5:
- Remove system_manager_s10.h and use system_manager_soc64.h.
v4:
- Change prefix from SYSMGR_S10* to SYSMGR_
On 11/26/19 4:40 AM, Masahiro Yamada wrote:
> On Thu, Nov 21, 2019 at 6:38 AM Marek Vasut wrote:
>>
>> The SoCFPGA Gen5 does not have a clock driver yet, let the NAND driver
>> work without a clock driver by falling back to the default frequencies.
>>
>> Signed-off-by: Marek Vasut
>> Cc: Masahiro
Move Stratix10 and Agilex common CONFIGs to socfpga_soc64_common.h.
Signed-off-by: Ley Foon Tan
---
...ratix10_socdk.h => socfpga_soc64_common.h} | 8 +-
include/configs/socfpga_stratix10_socdk.h | 193 +-
2 files changed, 7 insertions(+), 194 deletions(-)
copy include/con
Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Remove compatible "intel,sdr-ctl-agilex" from this patch.
v3:
- Change sdram_common.* to sdram_soc64.*
Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.
Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v5:
- Move CCU driver to DM.
--
Unlink test for FAT file system seems to fail at test_unlink2.
(When I added this test, I haven't seen any errors though.)
for example,
===8<===
fs_obj_unlink = ['fat', '/home/akashi/tmp/uboot_sandbox_test/128MB.fat32.img']
def test_unlink2(self, u_boot_console, fs_obj_unlink):
"""
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.
agilex-clock.h is from Linux commit ID cd2e1ad12247.
Signed-off-by: Chee Hong Ang
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Use agilex-clock.h from Linux instead of using stra
Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.
SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v4:
- Move SYSMGR_DMA* to firewall.c
v3
Hi Matthias,
On 24.11.2019 10:39, Matthias Brugger wrote:
> On 22/11/2019 14:40, Marek Szyprowski wrote:
>> On 20.11.2019 10:10, Matthias Brugger wrote:
>>> On 20/11/2019 02:57, Tom Rini wrote:
On Tue, Nov 19, 2019 at 05:02:34PM +0100, Matthias Brugger wrote:
> Please have a look at the b
Move Stratix10 and Agilex clock manager common code to new header file.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Move #include to top of header file.
v5:
- Revert CLKMGR_INTOSC_HZ to 460MHz.
---
.../include/mach/clock_manager_s10.h | 16 +++--
...
Add base address for Intel Agilex SoC.
Reuse base_addr_s10.h for Agilex, only one base address is
different from S10.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v2:
- Reuse base_addr_s10.h and add #ifdef Agilex for SOCFPGA_FW_MPU_DDR_SCR_ADDRESS
---
arch/arm/mach-socfpga/i
Add system manager support for Agilex.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v5:
- Remove system_manager_agilex.h and use system_manager_soc64.h directly.
v3:
- Change include filename to system_manager_soc64.h.
- Move to use defines instead of struct.
v2:
- Include s
Add SDRAM driver for Agilex SoC.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Add compatible "intel,sdr-ctl-agilex".
v4:
- Fixed checkpatch warnings
v3:
- Use sdmmc_soc64.*
- Change compatible string to use "intel" (intel,sdr-ctl-agilex).
Add reset manager support for Agilex.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v5:
- Remove reset_reset_manager_agilex.h and use reset_manager_soc64.h.
v3:
- Add reset_manager_soc64.h
- Convert to use defines instead of struct.
---
arch/arm/mach-socfpga/include/mach/rese
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Remove unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.
---
arch/arm/mach-socfpga/include/mach/cloc
Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Use new macro names from agilex-clock.h.
v4:
- Change to use SYSMGR_SOC64* prefix.
v3:
- Improved comm
Add build support for Agilex SoC.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v7:
- Move CONFIG_DW_WDT_CLOCK_KHZ to _soc64_common.h
- Use fdtimage filename from CONFIG_DEFAULT_DEVICE_TREE
v6:
- Include socfpga_soc64_common.h.
v5:
- Enable NCORE_CACHE
v3:
- Disable CONFIG_U
Add SPL support for Agilex SoC.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v5:
- Probe CCU driver with DM method.
v4:
- Move spl_early_init() to entry of board_init_f
- Add socfpga_get_manager_addr().
- Remove SYSMGR_DMA and SYSMGR_DMA_PERIPH, already set in firewall_setup(
Add device tree files for Agilex SoC platform.
socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains
Uboot specific DT properties.
socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux
(kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc)
Signed-off-by: Ley Foon Tan
Add socdk board support for Intel Agilex SoC
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
board/intel/agilex-socdk/MAINTAINERS | 7 +++
board/intel/agilex-socdk/Makefile| 7 +++
board/intel/agilex-socdk/socfpga.c | 7 +++
3 files changed, 21 insertions(+)
cr
The driver works fine with iMX6SX, add the missing compatible string.
Signed-off-by: Marek Vasut
Cc: Bin Meng
Cc: Fabio Estevam
Cc: Stefano Babic
---
drivers/pci/pcie_imx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 10b8fb4c88..c0
Hi Simon,
On Mon, Nov 25, 2019 at 12:11 PM Simon Glass wrote:
>
> Add support for some important configuration options and FSP memory init.
> The memory init uses swizzle tables from the device tree.
>
> Support for the FSP_S binary is also included.
>
> Bootstage timing is used for both FSP_M an
This patch adds support for iMX6SX MMDC into the DDR calibration
code. The only difference between MX6DQ and MX6SX is that the SX
has 2 SDQS registers, while the DQ has 8.
Signed-off-by: Marek Vasut
Cc: Eric Nelson
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/mach-imx/mx6/ddr.c | 18 +
# This is actually a resent patch of
# [1] https://lists.denx.de/pipermail/u-boot/2019-May/369170.html
Two test cases are added under test_fs_ext:
test case 10: for root directory
test case 11: for non-root directory
Those will verify a behavior fixed by the commits related to
root direct
Instead of explicitly setting up each SDQS register, use a loop.
No functional change.
Signed-off-by: Marek Vasut
Cc: Eric Nelson
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/mach-imx/mx6/ddr.c | 27 ---
1 file changed, 8 insertions(+), 19 deletions(-)
diff --git
Make the PMU LDO configuration interface available to board code,
so that board code can reconfigure the internal LDOs of the SoC.
Signed-off-by: Marek Vasut
Cc: Eric Nelson
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/include/asm/arch-mx6/sys_proto.h | 8
arch/arm/mach-imx/mx6/s
In preparation for use of DDR DRAM fine-tuning upon boot,
convert the board to SPL framework instead of using DCD
tables to bring up DRAM and pinmux.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Silvio Fricke
Cc: Stefano Babic
---
arch/arm/mach-imx/mx6/Kconfig | 1 +
board/sof
The fitImage support was enabled in the downstream U-Boot port and the
kernel images on the device are fitImage, yet this functionality is not
enabled in mainline U-Boot. Enable it.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Silvio Fricke
Cc: Stefano Babic
---
configs/vining_2000_defcon
The %08X format returns just zeroes with tiny printf, which is
horribly confusing, especially when debugging DRAM calibration
problems. Change the format to %08x (with lowercase x), which
behaves correctly with either implementation of printf in SPL.
Signed-off-by: Marek Vasut
Cc: Eric Nelson
Cc
Pull out the code turning SDQS pullups on and off into a separate
function, since it is replicated in two places in the code and it
is the single place in the entire function which is SoC dependent.
Signed-off-by: Marek Vasut
Cc: Eric Nelson
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/ma
Enable DRAM calibration in SPL to improve behavior of the board
in edge conditions of the thermal envelope of the board and make
it even more stable.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Silvio Fricke
Cc: Stefano Babic
---
board/softing/vining_2000/vining_2000.c | 5 +
configs
Ever since the conversion to DM PCI, the board was missing the PCIe DT
nodes, hence the PCI did not really work. Fill in the DT nodes and add
missing PCIe device reset.
Moreover, bring the PCIe power domain up before booting Linux. This is
mandatory to keep old broken vendor kernels working, as th
The board has both VDD_SOC_IN and VDD_ARM_IN rails connected to the same
PMIC rail, align the LDO voltages to avoid leaking inside the MX6SX SoC.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Silvio Fricke
Cc: Stefano Babic
---
board/softing/vining_2000/vining_2000.c | 3 +++
1 file change
Convert the board to ethernet DM support. Adjust board file accordingly,
as the board_eth_init() contains custom clock configuration required for
this board to work. Furthermore, enable FEC1 clock to make FEC1 work as
well.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Silvio Fricke
Cc: Stef
On Tue, Nov 26, 2019 at 5:23 PM Marek Vasut wrote:
>
> On 11/26/19 3:47 AM, Masahiro Yamada wrote:
> > On Thu, Nov 21, 2019 at 6:38 AM Marek Vasut wrote:
> >>
> >> Legacy kernel versions for SoCFPGA may not implement proper reset
> >> handling.
> >
> > What is "legacy kernel versions" ?
>
> Anythi
On Tue, Nov 26, 2019 at 9:22 AM Marek Vasut wrote:
>
> On 11/26/19 3:47 AM, Masahiro Yamada wrote:
> > On Thu, Nov 21, 2019 at 6:38 AM Marek Vasut wrote:
> >>
> >> Legacy kernel versions for SoCFPGA may not implement proper reset
> >> handling.
> >
> > What is "legacy kernel versions" ?
>
> Anythi
Update the binding file for gpio, it is just an alignment
with kernel v5.3.
The U-Boot code example for gpio-hog (not directly linked
to binding) is moved in a new file doc/README.gpio.
[commit 21676b706e99 ("gpio: fixes for gpio-hog support")
& 'commit 4762a9988ede ("gpio: add gpio-hog support")']
Remove the define GPIOD_REQUESTED as it is never used
and use BIT() macro for other defines.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- remove the unused GPIOD_REQUESTED
include/asm-generic/gpio.h | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/include/as
Add a simple pincontrol associated to the sandbox gpio driver,
that allows to check pin configuration with the command pinmux.
The pmux test is also updated to test behavior with 2 pincontrols.
Example to check LED pin configuration:
=> pinmux list
| Device| Driver
This commit manages the dir flags that can be used in gpio specifiers
to indicate if a pull-up resistor or pull-down resistor should be
enabled for output gpio (GPIO_PULL_UP, GPIO_PULL_DOWN) and the
Open Drain/Open Source configuration for input gpio
(GPIO_OPEN_DRAIN, GPIO_OPEN_SOURCE).
These flag
Add a helper function gpio_desc_init() to initialize the gpio descriptor;
with this function the flags will be always set to 0.
It wasn't the case before this patch in dm_gpio_lookup_name.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- add gpio descriptor initialization helper
drivers/g
Add tests for new API set_dir_flags and set_dir_flags and associated
code in gpio uclass.
Test support for new flags GPIO_OPEN_DRAIN, GPIO_OPEN_SOURCE
GPIO_PULL_UP and GPIO_PULL_DOWN.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- simplify sandbox GPIO driver: save dir_flags (GPIOD_...)
Hi,
I create this patchset to prepare alignment of stm32mp157c-ev1
device-tree with the linux kernel v5.4.
One node for touch screen support use the IRQ line configuration
using the new kernel binding introduced by the linux kernel
commit ede033e1e863c from v5.1 ('dt-bindings:
gpio: document the
Add param information in pin information output.
This update prepare unitary test for pin configuration
in pinctrl node.
Signed-off-by: Patrick Delaunay
Reviewed-by: Simon Glass
---
Changes in v2: None
drivers/pinctrl/pinctrl-sandbox.c | 30 ++
1 file changed, 30 i
Migrate pinctrl-generic to livetree:
- dev_for_each_property
- dev_read_prop_by_prop
- dev_read_string_count
- dev_read_string_index
and get rid of DECLARE_GLOBAL_DATA_PTR.
This patch solves the parsing issue during sandbox tests for pin
configuration (OF_LIVE is activated in sandbox_defconfig
and
Cleanup binding support, use the generic binding by default
(test u-class gpio_xlate_offs_flags function) and add
specific binding for added value.
Signed-off-by: Patrick Delaunay
Reviewed-by: Simon Glass
---
Changes in v2: None
arch/sandbox/dts/test.dts | 14 ++
dri
Add functions to iterate on all property with livetree
- dev_read_first_prop
- dev_read_next_prop
- dev_read_prop_by_prop
and
- ofnode_get_first_property
- ofnode_get_next_property
- ofnode_get_property_by_prop
For example:
struct ofprop property;
dev_for_each_property(property, config) {
This patch removes the ops get_open_drain/set_open_drain
and the API dm_gpio_get_open_drain/dm_gpio_set_open_drain.
The ops only provided in one driver (mpc8xxx gpio) and the
associated API is never called in boards.
This patch prepare a more generic set/get_dir_flags ops,
including the open drai
This commit extends the flags that can be used in GPIO specifiers to
indicate if a pull-up resistor or pull-down resistor should be
enabled.
It is the backport of linux commit ede033e1e863c ('dt-bindings:
gpio: document the new pull-up/pull-down flags')
from Thomas Petazzoni
and integrated in v5.
Convert 'pinctrl-single' using livetree functions
- dev_read_prop
- dev_read_u32_default
- dev_read_u32_array
- dev_read_bool
- dev_read_addr
and get rid of DECLARE_GLOBAL_DATA_PTR.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- use the dev_ API instead of ofnode_ function.
drivers/pinct
Add test for "pins" configuration in gpio uclass with set_state() ops
and test for generic parsing of pinconf_param array).
set_state() is called by:
- pinctrl_generic_set_state
|- pinctrl_generic_set_state_subnode
Signed-off-by: Patrick Delaunay
Reviewed-by: Simon Glass
---
Changes in v2: No
On 11/26/19 9:46 AM, Masahiro Yamada wrote:
> On Tue, Nov 26, 2019 at 5:23 PM Marek Vasut wrote:
>>
>> On 11/26/19 3:47 AM, Masahiro Yamada wrote:
>>> On Thu, Nov 21, 2019 at 6:38 AM Marek Vasut wrote:
Legacy kernel versions for SoCFPGA may not implement proper reset
handling.
>>>
>>
Hi Patrice,
> From: Patrice CHOTARD
> Sent: vendredi 15 novembre 2019 11:57
>
> This patch allows to fix the following compilation warning:
>
> = WARNING == This board
> does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please
> update the b
On Tue, Nov 26, 2019 at 9:24 AM Ley Foon Tan wrote:
>
> Add device tree files for Agilex SoC platform.
>
> socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains
> Uboot specific DT properties.
>
> socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux
> (kernel/git/dingu
Hi Patrick
On 11/6/19 4:16 PM, Patrick Delaunay wrote:
> Device tree and binding alignment with kernel v5.4-rc4
>
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/arm/dts/st-pincfg.h | 1 +
> arch/arm/dts/stm32429i-eval.dts | 25 ++---
> arch/arm/dts/stm32f429.dtsi
Hi Patrick
On 11/6/19 4:16 PM, Patrick Delaunay wrote:
> Device tree and binding alignment with kernel v5.3
> and converted to SPDX.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/arm/dts/stm32429i-eval.dts | 4 +-
> arch/arm/dts/stm32746g-eval.dts | 105 +--
On Tue, Nov 26, 2019 at 6:01 PM Marek Vasut wrote:
>
> On 11/26/19 9:46 AM, Masahiro Yamada wrote:
> > On Tue, Nov 26, 2019 at 5:23 PM Marek Vasut wrote:
> >>
> >> On 11/26/19 3:47 AM, Masahiro Yamada wrote:
> >>> On Thu, Nov 21, 2019 at 6:38 AM Marek Vasut wrote:
>
> Legacy kernel versi
On 11/26/19 10:07 AM, Masahiro Yamada wrote:
> On Tue, Nov 26, 2019 at 6:01 PM Marek Vasut wrote:
>>
>> On 11/26/19 9:46 AM, Masahiro Yamada wrote:
>>> On Tue, Nov 26, 2019 at 5:23 PM Marek Vasut wrote:
On 11/26/19 3:47 AM, Masahiro Yamada wrote:
> On Thu, Nov 21, 2019 at 6:38 AM Mar
> -Original Message-
> From: Simon Goldschmidt
> Sent: Tuesday, November 26, 2019 5:05 PM
> To: Tan, Ley Foon
> Cc: U-Boot Mailing List ; Marek Vasut
> ; Ley Foon Tan ; See, Chin Liang
> ; Ang, Chee Hong ;
> Chee, Tien Fong ; Dinh Nguyen
>
> Subject: Re: [PATCH v7 17/19] arm: dts: agil
On Tue, Nov 26, 2019 at 6:10 PM Marek Vasut wrote:
>
> On 11/26/19 10:07 AM, Masahiro Yamada wrote:
> > On Tue, Nov 26, 2019 at 6:01 PM Marek Vasut wrote:
> >>
> >> On 11/26/19 9:46 AM, Masahiro Yamada wrote:
> >>> On Tue, Nov 26, 2019 at 5:23 PM Marek Vasut wrote:
>
> On 11/26/19 3:47
On Mon, Nov 25, 2019 at 01:18:26PM -0300, Fabio Estevam wrote:
> Hi,
>
> Just tried to boot imx8mq-evk using latest U-Boot master and this is what I
> get:
>
> U-Boot SPL 2020.01-rc3-00070-g9a0cbae22a (Nov 25 2019 - 13:08:24 -0300)
> PMIC: PFUZE100 ID=0x10
> DDRINFO: start DRAM init
> DDRINFO:d
On Tue, Nov 26, 2019 at 5:25 PM Marek Vasut wrote:
>
> On 11/26/19 3:34 AM, Masahiro Yamada wrote:
> > On Thu, Nov 21, 2019 at 6:37 AM Marek Vasut wrote:
> >>
> >> While the Denali NAND is initialized by the BootROM in SPL, there
> >> are still a couple of settings which are missing. These can tri
On Fri, Nov 8, 2019 at 10:53 AM Ley Foon Tan wrote:
>
> Add an option for building cache drivers in SPL.
>
> Signed-off-by: Ley Foon Tan
> ---
> common/spl/Kconfig | 5 +
> drivers/Makefile | 1 +
> drivers/cache/Makefile | 2 +-
> 3 files changed, 7 insertions(+), 1 deletion(-)
>
Hi Marek,
On 26/11/2019 09:25, Marek Szyprowski wrote:
> Hi Matthias,
>
> On 24.11.2019 10:39, Matthias Brugger wrote:
>> On 22/11/2019 14:40, Marek Szyprowski wrote:
>>> On 20.11.2019 10:10, Matthias Brugger wrote:
On 20/11/2019 02:57, Tom Rini wrote:
> On Tue, Nov 19, 2019 at 05:02:34P
On Tue, Nov 26, 2019 at 5:04 PM Simon Goldschmidt
wrote:
>
> On Tue, Nov 26, 2019 at 9:24 AM Ley Foon Tan wrote:
> >
> > Add device tree files for Agilex SoC platform.
> >
> > socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains
> > Uboot specific DT properties.
> >
> > socfpga
On 11/26/19 10:24 AM, Masahiro Yamada wrote:
> On Tue, Nov 26, 2019 at 5:25 PM Marek Vasut wrote:
>>
>> On 11/26/19 3:34 AM, Masahiro Yamada wrote:
>>> On Thu, Nov 21, 2019 at 6:37 AM Marek Vasut wrote:
While the Denali NAND is initialized by the BootROM in SPL, there
are still a co
On 11/26/19 10:17 AM, Masahiro Yamada wrote:
> On Tue, Nov 26, 2019 at 6:10 PM Marek Vasut wrote:
>>
>> On 11/26/19 10:07 AM, Masahiro Yamada wrote:
>>> On Tue, Nov 26, 2019 at 6:01 PM Marek Vasut wrote:
On 11/26/19 9:46 AM, Masahiro Yamada wrote:
> On Tue, Nov 26, 2019 at 5:23 PM M
On Tue, Nov 26, 2019 at 10:37 AM Ley Foon Tan wrote:
>
> On Tue, Nov 26, 2019 at 5:04 PM Simon Goldschmidt
> wrote:
> >
> > On Tue, Nov 26, 2019 at 9:24 AM Ley Foon Tan wrote:
> > >
> > > Add device tree files for Agilex SoC platform.
> > >
> > > socfpga_agilex-u-boot.dtsi and socfpga_agilex_soc
Hello,
On Fri, Sep 13, 2019 at 07:40:22PM -0500, Joe Hershberger wrote:
> Part of the env cleanup moved this out of the environment code and into
> the net code. However, this helper is sometimes needed even when the net
> stack isn't included.
>
> Move the helper to lib/net_utils.c like it's sim
Hello,
On Tue, Nov 26, 2019 at 09:15:59AM +0100, Andre Heider wrote:
> That helper takes care of assembling the correct name and doesn't allow
> overwriting existing env vars, so drop the checks here.
>
> Signed-off-by: Andre Heider
> ---
> board/sunxi/board.c | 10 +-
> 1 file changed,
Hello Andre,
On Tue, Nov 26, 2019 at 09:16:00AM +0100, Andre Heider wrote:
> Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3,
> ship with the controller default address.
>
> Add a config option to fix it up so it can function properly.
I tried it on TBS A711 tablet that also ha
On Tue, Nov 26, 2019 at 11:46:33AM +0100, megous hlavni wrote:
> Hello Andre,
>
> On Tue, Nov 26, 2019 at 09:16:00AM +0100, Andre Heider wrote:
> > Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3,
> > ship with the controller default address.
> >
> > Add a config option to fix i
Hello,
On 11/21/19 12:00 AM, Giulio Benetti wrote:
This commit:
https://gitlab.denx.de/u-boot/u-boot/commit/d409c962169bd293e39386d0ddfa64d5222a3be4
causes build failure with ICACHE enabled. This is due to missing
invalidate_icache_all() stub. Let's add empty invalidate_icache_all() in
the case
This commit:
https://gitlab.denx.de/u-boot/u-boot/commit/d409c962169bd293e39386d0ddfa64d5222a3be4
causes build failure with ICACHE enabled. This is due to missing
invalidate_icache_all() stub. Let's add empty invalidate_icache_all() in
the case where ICACHE is not enabled.
Signed-off-by: Giulio Be
LX2160A PL011 UART driver fetch IP block values using
platform data from board file instead of device tree.
Modified UART nodes in device tree to disable state.
Signed-off-by: Vabhav Sharma
---
arch/arm/dts/fsl-lx2160a.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/fsl-
On Tue, Nov 26, 2019 at 09:22:38AM +0100, Jorge Ramirez-Ortiz, Foundries wrote:
> On 20/11/19 11:33:10, Jens Wiklander wrote:
> > On Wed, Nov 20, 2019 at 09:21:35AM +0100, Jorge Ramirez-Ortiz wrote:
> > > On 11/20/19 8:20 AM, Jens Wiklander wrote:
> > > > On Tue, Nov 19, 2019 at 06:21:34PM +0100, J
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