On the A33, uart0 is muxed on the PB pins. On SBCs these pins may be
available for use. Such is the case on the Sinlinx SinA33.
Set CONS_INDEX=1 to use uart0 as the console, matching the device tree.
Fixes: 7095f8641863 ("sunxi: Convert CONS_INDEX to Kconfig")
Signed-off-by: Chen-Yu Tsai
---
co
Dear Walter,
In message
you wrote:
>
> guess I'm not so lucky:
That was to be expected. The file was way too small for a complete
U-Boot - that would be in the order of 200 kB or more.
> I have figured out that central to the board is a TMS320DM350ZWK chip which
> seems to contain a fullblow
On 05/06/2017 01:05 AM, Marek Vasut wrote:
On 05/05/2017 07:55 PM, Jorge Ramirez wrote:
On 05/05/2017 05:34 PM, Marek Vasut wrote:
On 05/05/2017 04:32 PM, Tom Rini wrote:
On Thu, May 04, 2017 at 03:47:07PM +0200, Jorge Ramirez-Ortiz wrote:
CC'ing Marek...
Signed-off-by: Jorge Ramirez-Ortiz
Hi,
2017-05-07 3:21 GMT+08:00 Heiko Stuebner :
> Till now get_ldo_reg did a return &rk808_ldo[num - 1]; to return
> the ldo register offset but didn't take into account that its
> calling functions already created the ldo as ldo = dev->driver_data - 1.
>
> This resulted in the setting for ldo8 wri
Hi,
2017-05-06 3:28 GMT+08:00 Philipp Tomsich
:
> The recent changes to the RK808 driver caused our BSP to sync-abort in
> the regulator framework, when setting (or rather 'auto-setting') some
> of the LDOs.
>
> Turns out that the auto-allocation of the priv-structure in the rk8xx
> driver was nev
Hi,
2017-05-05 14:50 GMT+08:00 Kever Yang :
> The rk8xx_priv structure need to allocate for driver, or else
> it will cause data abort when CPU access it.
>
> This is a bug fix for below patch set:
> https://www.mail-archive.com/u-boot@lists.denx.de/msg247345.html
>
> Signed-off-by: Kever Yang
>
On 05/07/2017 12:56 PM, Jorge Ramirez wrote:
> On 05/06/2017 01:05 AM, Marek Vasut wrote:
>> On 05/05/2017 07:55 PM, Jorge Ramirez wrote:
>>> On 05/05/2017 05:34 PM, Marek Vasut wrote:
On 05/05/2017 04:32 PM, Tom Rini wrote:
> On Thu, May 04, 2017 at 03:47:07PM +0200, Jorge Ramirez-Ortiz w
Broadcom MIPS SoCs have one or two GPIO banks, depending on the number of
gpios present:
BCM6345 => 16 GPIOs / 1 bank
BCM6328 => 32 GPIOs / 1 bank
BCM6358 => 40 GPIOs / 2 banks
BCM63268 => 52 GPIOs / 2 banks
typedef struct GpioControl {
uint32 GPIODirHi; /* 0 */
uint32 GPIODi
This driver is based on linux/arch/mips/bcm63xx/gpio.c, simplified to allow
defining one or two independent banks for each Broadcom SoC.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: Introduce changes suggested by Simon Glass:
- Remove unneeded strdup.
drivers/gpio/
This board has several LEDs attached to gpio0.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/huawei,hg556a.dts | 73 +
configs/huawei_hg556a_ram_defconfig | 4 ++
2 files changed, 77 insertions(+)
dif
This SoC has one gpio bank divided into two 32 bit registers, with a total of
40 GPIOs.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/brcm,bcm6358.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/mips/dts/brc
This driver can control up to 24 LEDs and supports HW blinking and serial leds.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/brcm,bcm63268.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/a
This SoC has one gpio bank divided into two 32 bit registers, with a total of
52 GPIOs.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/brcm,bcm63268.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/mips/dts/br
This board has several LEDs attached to its BCM6328 led controller.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/comtrend,vr-3032u.dts| 43 ++
configs/comtrend_vr3032u_ram_defconfig | 4
2 files chan
This SoC has one gpio bank with a total of 32 GPIOs.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/brcm,bcm6328.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dts
This is a simplified version of linux/arch/mips/bcm63xx/clk.c
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: Introduce changes suggested by Simon Glass:
- Swap common.h include to the beginning.
- Add a more detailed description.
- Switch to fdtdec_get_bool().
dr
This board has several LEDs attached to its BCM6328 led controller.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/comtrend,ar-5387un.dts| 30 ++
configs/comtrend_ar5387un_ram_defconfig | 4
2 files change
This driver is a simplified version of linux/drivers/leds/leds-bcm6328.c,
simplified to remove HW leds and blink fallbacks.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: Introduce changes suggested by Simon Glass:
- Add DT binding file.
- Add features description.
BCM6328 supports controlling LEDs both by using the GPIO controller and the
LED controller. However, LED controller allows HW blinking and supports serial
LEDs.
v2: Introduce changes suggested by Simon Glass
Álvaro Fernández Rojas (5):
dm: led: add BCM6328 led driver
mips: bmips: add bcm6328-
This driver is a simplified version of linux/drivers/leds/leds-bcm6358.c
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: Introduce changes suggested by Simon Glass:
- Add DT binding file.
- Add features description.
- Switch to fdtdec_get_bool().
doc/device-tree-b
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/brcm,bcm6358.dtsi | 7 +++
include/dt-bindings/clock/bcm6358-clock.h | 24
2 files changed, 31 insertions(+)
creat
Broadcom MIPS SoCs have gated clock controllers which only allow enabling and
disabling each peripheral clock.
Changing clock rates is not possible on these SoCs.
v2: Introduce changes suggested by Simon Glass
Álvaro Fernández Rojas (5):
dm: clk: add BCM6345 clock driver
mips: bmips: add bcm6
This driver can control up to 24 LEDs and supports HW blinking and serial leds.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/brcm,bcm6328.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arc
BCM6358 supports controlling serial LEDs (74x164) both by using spi-gpio or
its LEDs controller.
v2: Introduce changes suggested by Simon Glass
Álvaro Fernández Rojas (3):
dm: led: add BCM6358 led driver
mips: bmips: add bcm6358-led driver support for BCM6358
mips: bmips: add NeufBox 4 (Ser
This serves as an example for bcm6358-leds.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/sfr,nb4-ser.dts | 93 +++
board/sfr/nb4_ser/Kconfig | 12 +
board/sfr/nb4_ser/MAINTAINERS | 6 +
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/brcm,bcm63268.dtsi | 13
include/dt-bindings/clock/bcm63268-clock.h | 52 ++
2 files changed, 65 insertions(
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/brcm,bcm6328.dtsi | 7 +++
include/dt-bindings/clock/bcm6328-clock.h | 25 +
2 files changed, 32 insertions(+)
crea
This driver can control up to 32 serial leds.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
arch/mips/dts/brcm,bcm6358.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi
index
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v2: no changes.
configs/comtrend_ar5387un_ram_defconfig | 1 +
configs/comtrend_vr3032u_ram_defconfig | 1 +
configs/huawei_hg556a_ram_defconfig | 1 +
configs/sfr_nb4-ser_ram_defconfig | 1 +
4 files changed, 4 inse
BCM6328 SoCs have power domain controllers which supports enabling and
disabling power for the different peripherals.
Álvaro Fernández Rojas (4):
dm: power: domain: add BCM6328 power domain driver
mips: bmips: add bcm6328-power-domain driver support for BCM6328
mips: bmips: add bcm6328-power
This allows controlling MISC IDDQ register on BCM6328 SoCs.
Signed-off-by: Álvaro Fernández Rojas
---
drivers/power/domain/Kconfig| 7 +++
drivers/power/domain/Makefile | 1 +
drivers/power/domain/bcm6328-power-domain.c | 83 +
3 files
This driver can control up to 32 power domains.
Signed-off-by: Álvaro Fernández Rojas
---
arch/mips/dts/brcm,bcm63268.dtsi | 7 ++
.../power-domain/bcm63268-power-domain.h | 25 ++
2 files changed, 32 insertions(+)
create mode 100644 include/
This driver can control up to 32 power domains.
Signed-off-by: Álvaro Fernández Rojas
---
arch/mips/dts/brcm,bcm6328.dtsi | 7 +++
.../dt-bindings/power-domain/bcm6328-power-domain.h | 21 +
2 files changed, 28 insertions(+)
create mode 100644 includ
Signed-off-by: Álvaro Fernández Rojas
---
configs/comtrend_ar5387un_ram_defconfig | 2 ++
configs/comtrend_vr3032u_ram_defconfig | 2 ++
2 files changed, 4 insertions(+)
diff --git a/configs/comtrend_ar5387un_ram_defconfig
b/configs/comtrend_ar5387un_ram_defconfig
index d613740..5b05fd2 100644
Hi Heiko,
Thanks for your comments.
On 05/05/2017 09:10 PM, Heiko Stuebner wrote:
Hi Kever,
Am Freitag, 5. Mai 2017, 10:39:35 CEST schrieb Kever Yang:
ARM64 is using 64bit address which address cell is 2 instead of 1,
update to support it when of-platdata enabled.
Signed-off-by: Kever Yang
this patch implement rockusb protocol on the device side. this is based on USB
download gadget infrastructure. the rockusb function implements the rd, wl, rid
commands. it can work with rkdeveloptool
Signed-off-by: Eddie Cai
Changes in v5:
rockusb is a protocol run between host pc and device. it help people get device
info, flash image to device. this patch implement rockusb on device side
Changes in v5:
-fix build error when build other board
-fix checkpatch error
Changes in v4:
-use enum instead of macro define
-move some structu
add a simple readme to introduce rockusb and tell people how to use it
Signed-off-by: Eddie Cai
Reviewed-by: Simon Glass
Changes in v5:
-none
Changes in v4:
-add some blank line to make it look better
Changes in v3:
-fix checkp
this patch add rockusb command. the usage is
rockusb
e.g. rockusb 0 mmc 0
Signed-off-by: Eddie Cai
Reviewed-by: Simon Glass
Changes in v5:
-none
Changes in v4:
-move USB_FUNCTION_ROCKUSB to drivers/usb/gadget/Kconfig
-modify the dependence
Changes in v3:
-fix comment from Simon and Lukasz
this patch enable rockusb support on rk3288 based device.
Signed-off-by: Eddie Cai
Changes in v5:
-none
Changes in v4:
-move to rk3288_common.h
Changes in v3:
-move to defconfig
---
include/configs/rk3288_common.h | 4
1
On Wed, May 03, 2017 at 11:36:06AM +0530, Jagan Teki wrote:
>On Thu, Apr 13, 2017 at 11:39 AM, Peng Fan wrote:
>> Add the Kconfig entry for SOFT_SPI which uses gpio to simulate the
>> SPI signals. We use it for accessing 74x164 on some i.MX boards.
>>
>> Signed-off-by: Peng Fan
>> Cc: Jagan Teki
Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).
Prior to this fix the blue USB port on the Minnowboard
Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
wrong. Correct value should be added by 0x2000, but since they
are supposed to be 'mode-gpio', 'pad-offset' is not needed at all.
Signed-off-by: Bin Meng
---
arc
On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote:
> On 05/05/2017 12:26 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Convert Macro #define configuration to Kconfig method. All FPGA
> > devices
> > enable configuration based on CONFIG_FPGA_ALTERA.
> >
> > Signed-o
On Mon, Apr 10, 2017 at 8:38 AM, Simon Glass wrote:
> Convert the pci_mmc driver over to driver model and migrate all x86 boards
> that use it.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/Kconfig | 1 +
> arch/x86/cpu/baytrail/valleyview.c | 12 --
> arch/x86/cpu/qua
On Mon, May 8, 2017 at 11:10 AM, Bin Meng wrote:
> On Mon, Apr 10, 2017 at 8:38 AM, Simon Glass wrote:
>> Convert the pci_mmc driver over to driver model and migrate all x86 boards
>> that use it.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> arch/Kconfig | 1 +
>> arch/x
On Jum, 2017-05-05 at 13:14 +0200, Marek Vasut wrote:
> On 05/05/2017 12:26 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Adding the Arria10 FPGA manager program assembly driver which can
> > be used
> > to feed bitstream into FPGA manager for configuring FPGA.
> >
>
On Jum, 2017-05-05 at 13:09 +0200, Marek Vasut wrote:
> On 05/05/2017 12:26 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Remove unused passing parameter of socfpga_bridges_reset function
> > in
> > SoCFPGA Arria10.
> So how do you un-reset the bridges if you drop this
On Jum, 2017-05-05 at 13:13 +0200, Marek Vasut wrote:
> On 05/05/2017 12:26 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Move FPGA driver which is Gen5 specific code into Gen5 files.
> > No functional change.
> It's a driver, so it should stay in drivers/ . If you nee
On 08.05.2017 04:52, Bin Meng wrote:
Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).
Prior to this fi
On 08.05.2017 04:52, Bin Meng wrote:
Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
wrong. Correct value should be added by 0x2000, but since they
are supposed to be 'mode-gpio', 'pad-offset' is not needed at a
The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt.
This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.
Signed-off-by: Stefan Roese
Cc: Natha
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