Dear Tom,
In message <20151015004002.GX23893@bill-the-cat> you wrote:
>
> I'm just not sure what to do about CONFIG_API some days. I know one use
> case is for GRUB but I'd like to move away from that if possible
> (distros should be doing the generic distro bits and extlinux.conf).
> After that
Hi york,
The earlier SoC is just LS1021a rev1.0, but rev1.0 haven't delivery to the
customer.
Also the rev1.0 has since gone out of production.
So we don't have necessary to support rev1.0 because no one will or possibly to
use rev1.0.
Best Regards,
Yuan Yao
> -Original Message-
> From
On 15/10/2015 06:00, Scott Wood wrote:
> On Wed, 2015-10-14 at 13:27 +0200, Albert ARIBAUD wrote:
>> On Wed, 14 Oct 2015 13:21:41 +0200, Albert ARIBAUD (3ADEV)
>> wrote:
>>> Hello Stefan,
>>>
>>> On Tue, 13 Oct 2015 22:11:42 -0700, Stefan Agner
>>> wrote:
This resyncs the driver changes with
Hi Jagan,
during bringing up QSPI within SPL on my ZYNQ ZC702 board i made some
review of your code.
Have a look.
On 01.09.2015 08:11, Jagan Teki wrote:
Added zynq qspi controller driver for Xilinx Zynq APSOC,
this driver is driver-model driven with devicetree support.
(...)
+
+/* zynq qsp
On 13/10/2015 16:01, Fabio Estevam wrote:
> PCI driver currently hangs on mx6qp.
>
> Toggle the reset bit with the appropriate timings to fix the issue.
>
> Based on the FSL kernel driver implementation.
>
> Signed-off-by: Fabio Estevam
> ---
> Changes since v3:
> - Remove blank line from commi
From: Pratiyush Mohan Srivastava
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava
---
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 4 +++-
ar
On 14/10/2015 04:54, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Commit 3f353cecc ("vf610: refactor DDRMC code") changed the original
> bstlen field from 3 to 0.
>
> Restore the original value for proper behaviour.
>
> Based on the patch from Anthony Felice
> for the vf610twr board.
>
> Re
Hi Wolfgang, Tom,
On Thu, Oct 15, 2015 at 9:28 AM, Wolfgang Denk wrote:
> Dear Tom,
>
> In message <20151015004002.GX23893@bill-the-cat> you wrote:
>>
>> I'm just not sure what to do about CONFIG_API some days. I know one use
>> case is for GRUB but I'd like to move away from that if possible
>>
Hi Stefan,
On 14/10/2015 19:58, Stefan Agner wrote:
> Currently, the device tree relocation is disabled, likely to
> keep some DDR3 RAM at the end for Cortex-M4 firmwares. This
> can be archived using bootm_size, which limits the image
> processing range of the boot commands.
>
> Move the device
From: Pratiyush Mohan Srivastava
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivas
Hi Tom,
I have a couple of last-minute fixes for the vfr610twr. Please pull them
from u-boot-imx, thanks !
The following changes since commit 61903b759aa336d798da49d884467219796817ff:
imximage: fix commands other than write_data (2015-10-07 13:43:15 +0200)
are available in the git repository
Add i.MX6DQP-Sabresd board support:
1. set fdt_file according to board_rev which is set at runtime.
2. Add mx6dqp_ddr_ioregs and calibration value for this board.
Signed-off-by: Peng Fan
Cc: Stefano Babic
Cc: Fabio Estevam
---
Before this patch needs to apply "pci: pcie_imx: Fix hang on mx6qp"
This macro is not needed, since gd->ram_size is assigned value using
function imx_ddr_size().
Signed-off-by: Peng Fan
Cc: Stefano Babic
Cc: Fabio Estevam
---
include/configs/mx6sabresd.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabres
Drop duplicated debug info for tcl.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/cpu/armv7/mx6/ddr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 6b039e4..567ddc4 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/ar
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in
SD boot now. For the customer's demand, QSPI needs to be supported in SD
boot too.
This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is
used t
On 10/14/2015 11:54 PM, York Sun wrote:
>
>
> On 09/16/2015 03:22 AM, Horia Geantă wrote:
>> Enable snooping for CAAM read & write transactions by
>> programming the SCFG snoop configuration register:
>> SCFG_SNPCNFGCR[SECRDSNP]
>> SCFG_SNPCNFGCR[SECWRSNP]
>>
>> Signed-off-by: Horia Geantă
>> Re
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava
---
README
Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]
Signed-off-by: Horia Geantă
Reviewed-by: Zhengxiong Jin
---
v2 - moved initialization in arch_cpu_init (instead of board_early_init_f),
as s
Hi Bin,
On 14 October 2015 at 03:01, Bin Meng wrote:
>
> In sipi_vector.S, cpu_index (passed as %eax) is wrongly overwritten
> by the ap_init() function address. Correct it.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/sipi_vector.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions
Hi Stefano,
On Thu, Oct 15, 2015 at 5:50 AM, Stefano Babic wrote:
> Thanks Fabio - as fix, I pick it up for the release.
I don't see this one included in your pull request for Tom.
Thanks
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On Thu, Oct 15, 2015 at 7:05 AM, Peng Fan wrote:
> This macro is not needed, since gd->ram_size is assigned value using
> function imx_ddr_size().
>
> Signed-off-by: Peng Fan
> Cc: Stefano Babic
> Cc: Fabio Estevam
Reviewed-by: Fabio Estevam
___
U-B
The current sparse image format parser is quite tangled, with a lot of
code duplication.
Start refactoring it by moving the header parsing function to a function
of its own.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom Rini
---
common/aboot.c | 45 -
The current sparse image parser relies heavily on the MMC layer, and
doesn't allow any other kind of storage medium to be used.
Rework the parser to support any kind of storage medium, as long as there
is an implementation for it.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom Rini
---
common/a
The functions and a few define to generate a fastboot message to be sent
back to the host were so far duplicated among the users.
Move them all to a common place.
Signed-off-by: Maxime Ripard
---
common/aboot.c | 32 ++---
common/fb_mmc.c
Hi everyone,
Here is the second attempt at getting fastboot flashing functions
working on top of a NAND, for arbitraly large images.
While the NAND support itself was quite easy to do, the support for
the Android sparse images was quite difficult to add, and ended up
being a quite huge refactorin
The current error message in get_part if CONFIG_MTDPARTS is disabled is
"offset is not a number" which is confusing and doesn't help at all.
Change that for something that might give a hint on what's going on.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom Rini
---
drivers/mtd/mtd_uboot.c | 2 +
The fastboot client will split the sparse images into several chunks if the
image that it tries to flash is bigger than what the device can handle.
In such a case, the bootloader is supposed to retain the last offset to
which it wrote to, so that it can resume the writes at the right offset
when f
The fastboot flash command that writes an image to a partition works in
several steps:
1 - Retrieve the maximum size the device can download through the
"max-download-size" variable
2 - Retrieve the partition type through the "partition-type:%s" variable,
that indicates whether or not the
So far the fastboot code was only supporting MMC-backed devices for its
flashing operations (flash and erase).
Add a storage backend for NAND-backed devices.
Signed-off-by: Maxime Ripard
---
common/Makefile | 7 +-
common/fb_nand.c| 195
To check the alignment of the image blocks to the storage blocks, the
current code uses a convoluted syntax, while a simple mod also does the
work.
Signed-off-by: Maxime Ripard
---
common/aboot.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/common/aboot.c b
Some devices might need to do some per-partition initialization
(ECC/Randomizer settings change for example) before actually accessing it.
Add some hooks before the write and erase operations to let the boards
define what they need to do if needed.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom R
The chunk parsing code was duplicating a lot of code among the various
chunk types, while all of them could be covered by generic and simple
functions.
Refactor the current code to reuse as much code as possible and hopefully
make the chunk parsing loop more readable and concise.
Signed-off-by: M
The Cubietruck has a mini-USB connector that can be used to power up the
board and as an OTG connector.
Since we have already some USB host-only ports right beside this one,
enable it in gadget mode
Signed-off-by: Maxime Ripard
---
configs/Cubietruck_defconfig | 5 +
1 file changed, 5 inser
The A13-Olinuxino has a mini-USB connector that can be used to power up
the board and as an OTG connector.
Since we have already some USB host-only ports right beside this one,
enable it in gadget mode
Signed-off-by: Maxime Ripard
---
configs/A13-OLinuXino_defconfig | 3 +++
1 file changed, 3 i
The Android sparse image format is currently supported through a file
called aboot, which isn't really such a great name, since the sparse image
format is only used for transferring data with fastboot.
Rename the file and header to a file called "sparse", which also makes it
consistent with the he
When using the fastboot boot command, the image sent to U-Boot will be an
Android boot image. If the support is missing, that won't obviously work,
so we need it in our configuration.
Signed-off-by: Maxime Ripard
---
include/configs/sunxi-common.h | 1 +
1 file changed, 1 insertion(+)
diff --gi
On 15/10/2015 14:23, Fabio Estevam wrote:
> Hi Stefano,
>
> On Thu, Oct 15, 2015 at 5:50 AM, Stefano Babic wrote:
>
>> Thanks Fabio - as fix, I pick it up for the release.
>
> I don't see this one included in your pull request for Tom.
>
Aargh ! Thanks for noting this, I am fixing it.
Regar
On Wed, Sep 30, 2015 at 09:15:58PM +0900, Masahiro Yamada wrote:
> Signed-off-by: Masahiro Yamada
Applied to u-boot/master, thanks!
--
Tom
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On Thu, Oct 15, 2015 at 11:32:51AM +0200, Stefano Babic wrote:
> Hi Tom,
>
> I have a couple of last-minute fixes for the vfr610twr. Please pull them
> from u-boot-imx, thanks !
>
> The following changes since commit 61903b759aa336d798da49d884467219796817ff:
>
> imximage: fix commands other t
Hi Tom,
On 15/10/2015 14:43, Tom Rini wrote:
> On Thu, Oct 15, 2015 at 11:32:51AM +0200, Stefano Babic wrote:
>
>> Hi Tom,
>>
>> I have a couple of last-minute fixes for the vfr610twr. Please pull them
>> from u-boot-imx, thanks !
>>
>> The following changes since commit 61903b759aa336d798da49d88
Hello Thierry,
On Thu, 20 Aug 2015 11:52:13 +0200, Thierry Reding
wrote:
> From: Thierry Reding
>
> Use the inner shareable attribute for memory, which makes more sense
> considering that this code is called when caches are being enabled.
>
> Cc: Albert Aribaud
> Cc: Marc Zyngier
> Signed-of
On Thu, Oct 15, 2015 at 02:49:29PM +0200, Stefano Babic wrote:
> Hi Tom,
>
> On 15/10/2015 14:43, Tom Rini wrote:
> > On Thu, Oct 15, 2015 at 11:32:51AM +0200, Stefano Babic wrote:
> >
> >> Hi Tom,
> >>
> >> I have a couple of last-minute fixes for the vfr610twr. Please pull them
> >> from u-boot
On Tue, Oct 13, 2015 at 11:01:27AM -0300, Fabio Estevam wrote:
> PCI driver currently hangs on mx6qp.
>
> Toggle the reset bit with the appropriate timings to fix the issue.
>
> Based on the FSL kernel driver implementation.
>
> Signed-off-by: Fabio Estevam
> Acked-by: Stefano Babic
Applied
On Tue, Oct 13, 2015 at 01:57:16PM +0530, Mugunthan V N wrote:
> With DM_GPIO, gpio parameters like ACTIVE_(LOW/HIGH) are to be
> parsed in xlate gpio drivers-ops. Since xlate is not implemented
> in omap_gpio driver, the driver considers all gpio to be
> ACTIVE_HIGH which is the default case and
On Tue, Oct 13, 2015 at 02:02:29PM +0530, Mugunthan V N wrote:
> Currently omap_hsmmc driver doesn't use sdcd pin to detect
> whether the card is present or not. Instead the same pin is used
> as GPIO to detect card presence. So change the pin mux mode from
> mmc0_sdcd to gpio0_6.
>
> Signed-off-
From: Mingkai Hu
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- No change.
V2:
- Create include/fsl_csu
get_clocks() should not be limited by ESDHC.
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- Removed defines in PPC configs that have no need to use.
V2:
- No change.
common/board_f.c | 2 +-
include/configs/colibri_vf.h | 1 +
include/configs/ls
Hi all,
Here are the main changes for v5, please help to review.
- Wrap up the in_be32 and in_le32 to gur_in32/scfg_in32 for GUR/SCFG block
- Move DDR related macros moved out of #ifdef in config.h
- Move the mmu table to cpu.h
- Change commit message for patch: armv8/fsl_lsch3: Change arch to
From: Hou Zhiqiang
The Frame Manager(FMan) is a big-endian peripheral, so the
registers, internal MURAM and BDs, which are allocated in main
memory and used to communication between core and FMan, should
be accessed in big-endian. The big-endian platforms can access
them directly as the code impl
From: Shaohui Xie
Use mb() instead of sync() to be compatible for both ARM and PowerPC.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- New patch. Separated from patch 'net: Move some header files to include/'
dr
From: Hou Zhiqiang
In convention, the '0' is a normal return value indicating there isn't
an error. While some functions of FMan IM driver treat '0' as an error
return value.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- New patch.
driv
From: Hou Zhiqiang
The FMan IM driver is developed for 32-bit platfroms and isn't
friendly to 64-bit platforms, so do the minimal refactor:
1. Refine the MURAM management and access.
2. Correct the initialization and operations for QDs and BDs.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Gong Q
From: Shaohui Xie
phy_shutdown should be wrapped by CONFIG_PHYLIB.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- New patch.
drivers/net/fm/eth.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net
From: Shaohui Xie
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- No change.
V2:
- No c
From: Shaohui Xie
QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.
Signed-off-by: Shaohui Xie
Signed-off-by: Mi
From: Mingkai Hu
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way fo
From: Shaohui Xie
MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
FMANs, so we should only define MDIO controller base on FMAN2 when there
is FMAN2.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
From: Mingkai Hu
LS1043ARDB Specification:
-
Memory subsystem:
* 2GByte DDR4 SDRAM (32bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G por
Signed-off-by: Gong Qianyu
Signed-off-by: Hou Zhiqiang
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
---
V5:
- No change.
V4:
- Add enable_layerscape_ns_access() in fsl-layerscape/spl.c
V3:
- No change.
V2:
- Removed unecessary NAND_PAGE_SIZE in ls1043a_common.h.
- Fixed "select SUP
From: Mingkai Hu
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang
Signed-off-by: Hou Zhiqiang
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- Move LS1043A ddr macros out of soc #ifdef.
- Mo
From: Yangbo Lu
This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- Use CONFIG_FSL_ESDHC to enable get_sdhc_freq().
- Merge lsch2 and lsch3 into layerscape.
V3:
- No change.
V2:
- No change.
.../arm/cpu/armv8/fsl-l
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- Squash the add cpld command patch to it.
V2:
- No change.
board/freescale/ls1043ardb/README| 1 +
board/freescale/ls1043ardb/cpld.c| 18 ++
board/freescale/ls1043ardb/cpld.h
From: Shaohui Xie
Signed-off-by: Hou Zhiqiang
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- Change arch to layerscape.
V3:
- No change.
V2:
- No change.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 12 +++
arch/arm/cp
On 13 October 2015 at 02:27, Mugunthan V N wrote:
> With DM_GPIO, gpio parameters like ACTIVE_(LOW/HIGH) are to be
> parsed in xlate gpio drivers-ops. Since xlate is not implemented
> in omap_gpio driver, the driver considers all gpio to be
> ACTIVE_HIGH which is the default case and fails to retu
Hi,
On Monday, 12 October 2015, Thomas Chou wrote:
>
> Export fdt_blob to the environment variable. So that we may
> use it to boot Linux.
>
> Signed-off-by: Thomas Chou
> ---
> v2
> move the code to per board, nios2-generic.c.
> v3
> move the code to generic, board_r.c.
>
> common/board_r.
Hello Alison,
Sorry for the late comment.
On Wed, 9 Sep 2015 10:22:02 +0800, Alison Wang
wrote:
> When building u-boot with the latest Linaro toolchain, such as
> gcc-linaro-4.9, u-boot will hang at PCIE init on LS1021A platform.
> The issue is reported on
> http://comments.gmane.org/gmane.linux
On Fri, Oct 9, 2015 at 3:09 PM, Liviu Dudau wrote:
> Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
> Declare a secondary memory bank and set the sizes correctly.
>
> Signed-off-by: Liviu Dudau
Reviewed-by: Linus Walleij
Yours,
Linus Walleij
___
On Wednesday, October 14, 2015 at 06:32:42 PM, Pavel Machek wrote:
> On Mon 2015-10-12 09:59:57, dingu...@opensource.altera.com wrote:
> > From: Dinh Nguyen
> >
> > Update the L2 AUX CTRL settings for the SoCFPGA.
> >
> > Enabling D and I prefetch bits helps improve SDRAM performance on the
> >
The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features
1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir receiver,
stereo headphone jack and hdmi video output.
The dts changes are identical to the dts files submitted upstream.
A few notes on the use if dldo and aldo reg
Signed-off-by: Hans de Goede
---
board/sunxi/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index c6371ea..dd27487 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -29,11 +29,11 @@ F: configs/
On Fri, Oct 9, 2015 at 3:09 PM, Liviu Dudau wrote:
> Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
> in order for the Linux kernel to be able to enumerate the bus. Add
> support code here that enables the host bridge, trains the links and
> sets up the Address Translati
From: Dinh Nguyen
Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.
Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has th
On Wed, Oct 14, 2015 at 11:31 AM, Pavel Machek wrote:
> On Mon 2015-10-12 09:59:56, dingu...@opensource.altera.com wrote:
>> From: Dinh Nguyen
>>
>> s/L310_SHARED_ATT_OVERRIDE_ENABLE/PL310_SHARED_ATT_OVERRIDE_ENABLE
>>
>> Signed-off-by: Dinh Nguyen
>
> Well, in kernel, pl310 -related registers a
On 10/15/2015 09:32 AM, Marek Vasut wrote:
> On Wednesday, October 14, 2015 at 06:32:42 PM, Pavel Machek wrote:
>> On Mon 2015-10-12 09:59:57, dingu...@opensource.altera.com wrote:
>>> From: Dinh Nguyen
>>>
>>> Update the L2 AUX CTRL settings for the SoCFPGA.
>>>
>>> Enabling D and I prefetch bits
On Tue, 2015-10-06 at 11:17 +, Joakim Tjernlund wrote:
> On Thu, 2015-10-01 at 08:57 +, Joakim Tjernlund wrote:
> > On Wed, 2015-09-30 at 21:35 +0200, Marek Vasut wrote:
> > > On Wednesday, September 30, 2015 at 08:24:10 PM, Andy Fleming wrote:
> > >
> > > Hi!
> > >
> > > > On Thu, Oct 23
On 10/15/2015 02:14 AM, Prabhakar Kushwaha wrote:
> From: Pratiyush Mohan Srivastava
>
> LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
> personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
>
> So renaming existing LS2085A code base to reflect LS
On 10/15/2015 09:25 AM, York Sun wrote:
>
>
> On 10/15/2015 02:14 AM, Prabhakar Kushwaha wrote:
>> From: Pratiyush Mohan Srivastava
>>
>> LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
>> personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
>>
>>
>> Yuantian,
>>
>> Please explain more why the second stage u-boot is reserved? Wouldn't
>> Linux overwrite the memory?
>>
> If both CONFIG_DEEP_SLEEP and CONFIG_SD_BOOT are defined,
> The DDR memory the second stage uboot occupied whould be reserved.
> It is achieved in commit: 41ba57d0c which is
On 10/15/2015 12:55 AM, Yuan Yao-B46683 wrote:
> Hi york,
>
> The earlier SoC is just LS1021a rev1.0, but rev1.0 haven't delivery to the
> customer.
> Also the rev1.0 has since gone out of production.
> So we don't have necessary to support rev1.0 because no one will or possibly
> to use rev1.
On 09/17/2015 03:46 AM, Aneesh Bansal wrote:
> The SEC driver code has been cleaned up to work for 64 bit
> physical addresses and systems where endianess of SEC block
> is different from the Core.
> Changes:
> 1. Descriptor created on Core is modified as per SEC block
>endianness before the
On Thu, 15 Oct 2015 16:42:19 +0200
Linus Walleij wrote:
> On Fri, Oct 9, 2015 at 3:09 PM, Liviu Dudau wrote:
>
> > Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
> > in order for the Linux kernel to be able to enumerate the bus. Add
> > support code here that enables t
On Thursday, October 15, 2015 at 05:04:38 PM, Dinh Nguyen wrote:
Hi!
> >>> diff --git a/arch/arm/include/asm/pl310.h
> >>> b/arch/arm/include/asm/pl310.h index 18b90b7..7a11405 100644
> >>> --- a/arch/arm/include/asm/pl310.h
> >>> +++ b/arch/arm/include/asm/pl310.h
> >>> @@ -17,6 +17,8 @@
> >>>
On Thu, Oct 15, 2015 at 1:08 PM, Marek Vasut wrote:
> On Thursday, October 15, 2015 at 05:04:38 PM, Dinh Nguyen wrote:
>
> Hi!
>
>> >>> diff --git a/arch/arm/include/asm/pl310.h
>> >>> b/arch/arm/include/asm/pl310.h index 18b90b7..7a11405 100644
>> >>> --- a/arch/arm/include/asm/pl310.h
>> >>> +++
On Thu, 2015-10-15 at 16:33 +0200, Hans de Goede wrote:
> The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features
> 1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir
> receiver,
> stereo headphone jack and hdmi video output.
>
> The dts changes are identical to the dts fi
On Thu, 2015-10-15 at 14:34 +0200, Maxime Ripard wrote:
> When using the fastboot boot command, the image sent to U-Boot will be an
> Android boot image. If the support is missing, that won't obviously work,
obviously won't ??
> so we need it
On 10/15/2015 06:02 AM, Gong Qianyu wrote:
> From: Mingkai Hu
>
> There are two LS series processors are built on ARMv8 Layersacpe
> architecture currently, LS2085A and LS1043A. They are based on
> ARMv8 core although use different chassis, so create fsl-layerscape
> to refactor the common code
The current fastboot support assumes that CONFIG_FASTBOOT_FLASH implies
that we have an MMC in our system, which might not be the case if we have
some other storage device.
Change the configuration option protecting that call to
FASTBOOT_FLASH_MMC_DEV, that makes much more sense.
Signed-off-by: M
Not all sunxi boards have an MMC embedded. Switching to the Kconfig option
will allow to enable or disable the support in each boards' defconfig.
Signed-off-by: Maxime Ripard
---
board/sunxi/Kconfig| 4
drivers/mmc/Kconfig| 2 +-
include/configs/sunxi-common.h | 8 ++
Add the latest kernel changes to the sun5i family DTSI.
Signed-off-by: Maxime Ripard
---
arch/arm/dts/sun5i-a10s.dtsi | 47 ---
arch/arm/dts/sun5i-a13.dtsi | 28 -
arch/arm/dts/sun5i-r8.dtsi | 59
Hi,
Here is a serie introducing the support for the Allwinner R8 and the
Nextthing's CHIP.
The only missing parts for now are the display on the composite
output and the NAND support that will come in due time.
Everything else should work just fine, including the USB gadget and
host support.
Le
Add a generic Kconfig option for the CONFIG_MMC option that was used before
in the configuration headers.
Since all the architectures need to be converted to that first, depend on
an non-existent config option that will be extended with architectures that
use that option.
Signed-off-by: Maxime Ri
The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
and two connectors to plug additional boards on top of it.
The DT is identical to the DT submitted to the upstream kernel.
Signed-off-by: Maxime Ripard
So far, even if CONFIG_MMC was not enabled the board code was trying to use
the MMC-related functions, resulting in linker errors.
Protect those calls by an ifdef.
Signed-off-by: Maxime Ripard
---
arch/arm/cpu/armv7/sunxi/board.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
Linux had a number of changes to the AXP209 DTSI. Sync ours.
Signed-off-by: Maxime Ripard
---
arch/arm/dts/axp209.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/axp209.dtsi b/arch/arm/dts/axp209.dtsi
index 24c935c72e5e..051ab3ba9a65 100644
--- a/arch/arm/dts/axp209.dt
Hi Yuan
On 15/10/15 12:40 PM, York Sun wrote:
On 10/15/2015 12:55 AM, Yuan Yao-B46683 wrote:
Hi york,
The earlier SoC is just LS1021a rev1.0, but rev1.0 haven't delivery to the
customer.
Also the rev1.0 has since gone out of production.
So we don't have necessary to support rev1.0 becaus
On Thu, Oct 15, 2015 at 03:52:08AM +0200, Andreas Färber wrote:
> Am 15.10.2015 um 02:40 schrieb Tom Rini:
> > On Thu, Oct 15, 2015 at 02:28:34AM +0200, Andreas Färber wrote:
> >> Am 12.10.2015 um 17:18 schrieb Tom Rini:
> >>> If you have a regression, speak up.
> >>
> >> For -rc4 I had reported th
Hello,
The following changes since commit 297faccca2235e359012118495b9b73451d54bb9:
Merge branch 'master' of git://www.denx.de/git/u-boot-imx (2015-10-13
08:37:38 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-arm master
for you to fetch changes up to b1964c72bdb9
On Tue, Oct 13, 2015 at 9:23 AM, Patrick Delaunay
wrote:
> code under flag CONFIG_PARTITION_TYPE_GUID
> add parameter guid to select partition type guid
>
> example of use with gpt command :
>
> partitions = uuid_disk=${uuid_gpt_disk};name=boot,start=0x4400,
> size=0x6bc00,uuid=${uuid_gpt_boot
On Thu, Oct 15, 2015 at 03:58:24PM -0500, Rob Herring wrote:
> On Tue, Oct 13, 2015 at 9:23 AM, Patrick Delaunay
> wrote:
> > code under flag CONFIG_PARTITION_TYPE_GUID
> > add parameter guid to select partition type guid
> >
> > example of use with gpt command :
> >
> > partitions = uuid_disk=$
On Thu, Oct 15, 2015 at 03:56:09PM +, Joakim Tjernlund wrote:
> On Tue, 2015-10-06 at 11:17 +, Joakim Tjernlund wrote:
> > On Thu, 2015-10-01 at 08:57 +, Joakim Tjernlund wrote:
> > > On Wed, 2015-09-30 at 21:35 +0200, Marek Vasut wrote:
> > > > On Wednesday, September 30, 2015 at 08:24
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