i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL.
Signed-off-by: Peng Fan
Cc: Stefano Babic
Cc: Tim Harvey
---
arch/arm/cpu/armv7/mx6/ddr.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> CONFIG_SPL_NAND_SUPPORT gets used via IS_ENABLED so it must be
> defined
> to 1, rather then just being defined.
>
> While at remove 2 other unused NAND related defines from sunxi
> -common.h.
>
> Signed-off-by: Hans de Goede
Acked-by:
Add LPDDR2 support:
1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2.
2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to
mx6_ddr3_cfg, but still keep it a single one for easy to choose
parameters for LPDDR2.
3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to ini
Enable CONFIG_SPL_FAT_SUPPORT to load u-boot.img from FAT partition.
Signed-off-by: Peng Fan
---
include/configs/mx6sxsabresd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 848bdcd..74d04a0 100644
--- a/include/configs/
Hi Siva,
On 13 August 2015 at 18:18, Siva Durga Prasad Paladugu
wrote:
>> >> >> Hi Zhejiang/Jagan,
>> >> >>
>> >> >> I think it would be good to extend this further to support 4-byte
>> >> >> addressing in u-boot also.
>> >> >> This would be based on the driver, We can get the data that
>> >> >>
Add SPL boot support for mx6slevk board.
1. Introduce a configuration file mx6slevk_spl_defconfig.
2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE.
3. Include imx6_spl.h and related SPL macro in mx6slevk.h.
4. select SUPPORT_SPL for TARGET_MX6SLEVK.
5. Add SPL board code
On Mon, 2015-08-17 at 15:22 +0800, Chen-Yu Tsai wrote:
>
> > +#define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16)
>
> Might want to mention this change (correct DMA type?) in the commit
> log.
Yes, would be good.
With that: Acked-by: Ian Campbell
_
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> There is no need to reset the nand chip for every ecc-block read.
>
> Signed-off-by: Hans de Goede
Acked-by: Ian Campbell
___
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On 17 August 2015 at 13:29, Vignesh R wrote:
> ti_qspi uses memory map mode for faster read. Enabling DMA will increase
> read speed by 3x @48MHz on DRA74 EVM.
>
> Signed-off-by: Vignesh R
> Reviewed-by: Jagan Teki
> ---
> drivers/spi/ti_qspi.c | 23 +++
> 1 file changed, 23
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> In syndrome mode we set the NFC_SEQ bit in the command register, so the
> spare-area register is not used. Also the value currently being written is
> actual wrong, the ecc sits at "column + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE"
> not just CO
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are
> actually using the nand.
>
> Signed-off-by: Hans de Goede
Acked-by: Ian Campbell
___
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U-Boot@lists.d
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> We use DMA for nand data transfers in the SPL, so make sure the DMA
> controller is enabled.
>
> Signed-off-by: Hans de Goede
Acked-by: Ian Campbell
___
U-Boot mailing list
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On 8/17/2015 1:48 PM, Jagan Teki wrote:
> On 17 August 2015 at 13:29, Vignesh R wrote:
>> ti_qspi uses memory map mode for faster read. Enabling DMA will increase
>> read speed by 3x @48MHz on DRA74 EVM.
>>
>> Signed-off-by: Vignesh R
>> Reviewed-by: Jagan Teki
>> ---
>> drivers/spi/ti_qspi.c
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> Turn off the nand and dma clocks when we're done with the nand, this
> puts the nand and dma controllers back into a clean state for when the
> kernel boots.
>
> Without this the kernel will not boot properly when it is build with
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> We are using dma, so we should flush the cache before starting the dma,
> and invalidate it once the dma is done.
>
> Things are working without this by mostly luck, but lets not rely on that.
>
> Signed-off-by: Hans de Goede
Acked-by: I
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> Sync the code for figuring out the ecc_mode and ecc_offset with the kernel
> code. Keeping this in sync seems like a good idea in general,
I agree. When doing this IME it is useful to include the last version
sync'd in, either as a code com
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> We currently only use the spl nand code to get u-boot itself, which
> _always_ is located on a syndrome partition. Once we figure out how
> we are going to store the u-boot env on nand, we may need non syndrome
> support, but even then there
Signed-off-by: Mingkai Hu
---
drivers/net/e1000.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index d5d48b1..e816410 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -4980,8 +4980,8 @@ e1000_configure_tx(struct
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> Other then having a few less chip-select lines the nand controller
> on sun4i, sun5i and sun7i is identical.
>
> Signed-off-by: Hans de Goede
> ---
> board/sunxi/board.c | 12 +---
> drivers/mtd/nand/Kconfig | 4 ++--
> 2 fi
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> Properly config page-size in the nand ctl register, it seems that things
> work fine without doing this, but still lets play it safe and properly
> set the page-size.
>
> Signed-off-by: Hans de Goede
Acked-by: Ian Campbell
__
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> Parametrize the lowlevel nand_read_page function, instead of directly
> using the CONFIG_foo settings for page-size, etc. there and add a few
> wrappers / helper functions for calling it.
>
> This is a preparation patch for adding auto-dete
Hi,
On 17-08-15 10:29, Ian Campbell wrote:
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.
Signed-off-by: Hans de Goede
---
board/sunxi/board.c | 12 +---
drivers
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> Auto detect the nand configuration parameters, like the BROM does.
>
> This allows us to get rid of various Kconfig settings, and is
> necessary to support generic boards like the mk802 which have seen
> many production runs with different
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> The BROM does not care / use bad page markings, instead it deals with
> any bad pages in the first erase-block by simply trying to load "boot0"
> from the first next erase-block.
"first/next"? Maybe, or maybe s/first //?
> This
On Mon, 2015-08-17 at 10:31 +0200, Hans de Goede wrote:
> Hi,
>
> On 17-08-15 10:29, Ian Campbell wrote:
> > On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> > > Other then having a few less chip-select lines the nand
> > > controller
> > > on sun4i, sun5i and sun7i is identical.
> > >
Hi Masahiro,
On 08/17/2015 08:51 AM, Masahiro Yamada wrote:
This file was accidentally added by commit 181bd9dc61d2 ("kconfig:
add config option for shell prompt").
Signed-off-by: Masahiro Yamada
---
include/configs/odroid_xu3.h.rej | 10 --
1 file changed, 10 deletions(-)
delete
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Monday, August 17, 2015 1:43 PM
> To: Siva Durga Prasad Paladugu
> Cc: Hou Zhiqiang; Stefan Roese; nofooter; York Sun; u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH V6] sf: Turn SPI flash chip into
On 17/08/2015 10:12, Peng Fan wrote:
> Enable CONFIG_SPL_FAT_SUPPORT to load u-boot.img from FAT partition.
>
> Signed-off-by: Peng Fan
> ---
> include/configs/mx6sxsabresd.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
2015-08-17 17:44 GMT+09:00 Przemyslaw Marczak :
> Hi Masahiro,
>
> On 08/17/2015 08:51 AM, Masahiro Yamada wrote:
>>
>> This file was accidentally added by commit 181bd9dc61d2 ("kconfig:
>> add config option for shell prompt").
>>
>> Signed-off-by: Masahiro Yamada
>> ---
>>
>> include/configs/od
Hi,
On 17-08-15 10:19, Ian Campbell wrote:
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
In syndrome mode we set the NFC_SEQ bit in the command register, so the
spare-area register is not used. Also the value currently being written is
actual wrong, the ecc sits at "column + CONFIG_NA
Hi Roy,
On Mon, 17 Aug 2015 09:30:38 +0100
Roy Spliet wrote:
> Hello,
>
> Reply in-line
>
> Op 17-08-15 om 08:34 schreef Boris Brezillon:
> > Hi Oliver,
> >
> > Sorry for the late reply (I was in vacation for the last 2 weeks)
> >
> > On Tue, 11 Aug 2015 14:16:52 +0200
> > Olliver Schinagl wr
Hi,
On 17-08-15 10:27, Ian Campbell wrote:
On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
We currently only use the spl nand code to get u-boot itself, which
_always_ is located on a syndrome partition. Once we figure out how
we are going to store the u-boot env on nand, we may need no
On 17 August 2015 at 14:26, Siva Durga Prasad Paladugu
wrote:
> Hi Jagan,
>
>> -Original Message-
>> From: Jagan Teki [mailto:jt...@openedev.com]
>> Sent: Monday, August 17, 2015 1:43 PM
>> To: Siva Durga Prasad Paladugu
>> Cc: Hou Zhiqiang; Stefan Roese; nofooter; York Sun; u-boot@lists.d
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Monday, August 17, 2015 2:42 PM
> To: Siva Durga Prasad Paladugu
> Cc: Stefan Roese; u-boot@lists.denx.de; Hou Zhiqiang; York Sun
> Subject: Re: [U-Boot] [PATCH V6] sf: Turn SPI flash chip into 3-Byte add
On Mon, Aug 17, 2015 at 4:59 PM, Masahiro Yamada
wrote:
> 2015-08-17 17:44 GMT+09:00 Przemyslaw Marczak :
>> Hi Masahiro,
>>
>> On 08/17/2015 08:51 AM, Masahiro Yamada wrote:
>>>
>>> This file was accidentally added by commit 181bd9dc61d2 ("kconfig:
>>> add config option for shell prompt").
>>>
>>
+Wolfgang
Hi Wolfgang,
On Sat, Aug 15, 2015 at 9:44 AM, Bin Meng wrote:
> Hi,
>
> I noticed that this morning when I do git fetch it always fails with
> "Connection reset by peer" message.
>
> $ git fetch x86
> fatal: read error: Connection reset by peer
>
> Also patchwork is not updating any ne
On 17 August 2015 at 14:44, Siva Durga Prasad Paladugu
wrote:
> Hi Jagan,
>
>> -Original Message-
>> From: Jagan Teki [mailto:jt...@openedev.com]
>> Sent: Monday, August 17, 2015 2:42 PM
>> To: Siva Durga Prasad Paladugu
>> Cc: Stefan Roese; u-boot@lists.denx.de; Hou Zhiqiang; York Sun
>>
From: Tang Yuantian
Freescale ARM-based Layerscape LS2085A contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2085aqds and ls2085ardb boards.
Signed-off-by: Tang Yuantian
---
v2:
- rebase to the
ti_qspi uses memory map mode for faster read. Enabling DMA will increase
read speed by 3x @48MHz on DRA74 EVM.
Signed-off-by: Vignesh R
Reviewed-by: Jagan Teki
---
* Added a TODO comment
drivers/spi/ti_qspi.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drive
On 17 August 2015 at 10:48, Bin Meng wrote:
> Hi Igor,
>
> On Mon, Aug 17, 2015 at 3:10 PM, Stoppa, Igor wrote:
[...]
>> One other thing that I haven't fully investigated yet (so maybe it's
>> already explained elsewhere) is: after the application/payload is
>> built for x86 EFI,
>> how to deal
On 17 August 2015 at 12:48, Stoppa, Igor wrote:
> I'm referring to this:
>
> http://www.denx.de/wiki/view/DULG/UBootEnvVariables
>
> I thought it would become a partition, but maybe I've assumed too much
> and it is implemented in some other way?
ah, I see now that I should use CONFIG_ENV_IS_IN_
From: Tang Yuantian
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
Signed-off-by: Tang Yuantian
---
v2:
- rebase to late
BAR and spi_flash_cmd_wait_ready are updated to make more
module to add new status checks.
Changes for v2:
- Update bank_sel for non-bar case.
- split the spi_flash_cmd_wait_ready logic into SR and FSR patches.
Clone spi-nor branch u-boot-spi.git repo for changes
http://git.denx.de/?p=u-boot/u-bo
Use the flash->flags for generic usage, not only for dm-spi-flash,
this will be used for future flag additions.
Signed-off-by: Jagan Teki
Cc: Bin Meng
---
drivers/mtd/spi/sf_internal.h | 4
drivers/mtd/spi/sf_probe.c| 6 ++
include/spi_flash.h | 4 ++--
3 files changed, 8
Optimized spi-flash bar writing code and also removed
unnecessary bank_sel in read_ops.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
drivers/mtd/spi/sf_ops.c | 41 +
1 file changed, 13 insertions(+), 28 d
If computed bank_sel is same as flash->bank_curr which is
computed at probe time, then return the bank_sel instead of zero.
Signed-off-by: Jagan Teki
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
drivers/mtd/spi/sf_ops.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Add spi_flash_read_bar function for reading bar and discovering
bar commands at probe time.
Signed-off-by: Jagan Teki
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
drivers/mtd/spi/sf_probe.c | 54 ++
1 file changed, 35 insertions(+), 19 deletio
Current flash wait_ready logic is not modular to add new
register status check, hence few of the logic is used from
Linux spi-nor framework.
Below are the sf speed runs with 'sf update' on whole flash, 16MiB.
=> sf update 0x100 0x0 0x100
device 0 whole chip
16777216 bytes written, 0 bytes ski
- Removed unneeded inclusion of header files
- Add "Xilinx" on license text
Signed-off-by: Jagan Teki
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
drivers/spi/zynq_spi.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_sp
This patch adds flag status register reading support to
spi_flash_cmd_wait_ready.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Marek Vasut
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Cc: Stefan Roese
Cc: Tom Warren
Cc: Bin Meng
Cc: Tom Rini
Cc: Hou Zhiqiang
Tested-by: Jagan Teki
--
On 17 August 2015 at 08:33, Hou Zhiqiang wrote:
> Hello Jagan,
>
>> -Original Message-
>> From: Jagan Teki [mailto:jt...@openedev.com]
>> Sent: 2015年8月16日 16:50
>> To: u-boot@lists.denx.de; Hou Zhiqiang-B48286; Sun York-R58495
>> Cc: Jagan Teki
>> Subject: Re: [PATCH 0/6] sf: BAR/wait_read
The existing i8042 keyboard controller driver has some issues.
First of all, it does not issue a self-test command (0xaa) to the
controller at the very beginning. Without this, the controller
does not respond any command at all. Secondly, it initializes
the configuration byte reigster to turn on ke
This commit cleans up the existing i8042 driver by:
- Reorder those static function so that their declarations can be removed
- Remove unused routines i8042_flush() and i8042_disable()
- Remove unused CONFIG_USE_CPCIDVI wrapped codes
- Remove __weak board_i8042_skip()
- Rename CamelCase variables t
Add an api to enable and configure the integrated keyboard controller
on SMSC LPC47m superio chipset. It also adds several macros to help
future extension.
Signed-off-by: Bin Meng
---
arch/x86/include/asm/ibmpc.h | 3 +++
drivers/misc/smsc_lpc47m.c | 11 +++
include/smsc_lpc47m.h
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.
In order to make PS/2 keyboard work with
So far if CONFIG_VGA_AS_SINGLE_DEVICE is not defined, the VGA device
will try to initialize a keyboard device (for x86, it is i8042). But
if i8042 controller initialization fails (eg: there is no keyboard
connected to the PS/2 port), drv_video_init() just simply returns.
This kills the opportunity
Bootlog:
U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21)
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 33024000 Hz, block size 512
reading u-boot.img
reading u-boot.img
U-Boot
DEVDISRn registers provides a mechanism for gating clocks of IP blocks
that are not used. Here we implement hwconfig option to allow users
to disable unused peripherals on the board.
For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts,
User can enable CONFIG_FSL_DEVICE_DISABLE an
Hi Simon,
On Sat, Aug 15, 2015 at 3:07 PM, Bin Meng wrote:
> This adds a new driver to support National Semiconductor 16550
> compatible UART device with PCI interface. The initial support
> only adds device IDs for Intel Topcliff chipset UART devices.
>
> Signed-off-by: Bin Meng
> ---
>
> driv
Hi Simon,
On Sat, Aug 15, 2015 at 3:07 PM, Bin Meng wrote:
> With driver model pci conversion, the call to FspNotify was dropped.
> Now add this call back as this is required by the FSP spec.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/queensbay/tnc.c | 8 +++-
> 1 file changed, 7 in
On Mon, 2015-08-17 at 10:59 +0200, Hans de Goede wrote:
> Hi,
>
> On 17-08-15 10:19, Ian Campbell wrote:
> > On Sat, 2015-08-15 at 22:02 +0200, Hans de Goede wrote:
> > > In syndrome mode we set the NFC_SEQ bit in the command register,
> > > so the
> > > spare-area register is not used. Also the
Hi Tom,
I resynchronize the master branch this morning,
and only patch 7/7 of the series appear in u-boot/master;
Is it possible that patch 1/7 to 6/7 were not applied?
For your convenience this is a list of links to patchwork:
* http://patchwork.ozlabs.org/patch/500510/
* http://patchwork.ozlab
On Mon, Aug 17, 2015 at 11:34:59AM +, LEMIEUX, SYLVAIN wrote:
> Hi Tom,
>
> I resynchronize the master branch this morning,
> and only patch 7/7 of the series appear in u-boot/master;
>
> Is it possible that patch 1/7 to 6/7 were not applied?
>
> For your convenience this is a list of links
This patch fixes a potential NULL pointer dereference arising on
non-present/non-initialized xHCI controllers and adds some error
handling to xHCI code
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Radha Mohan Chintakuntla
---
Changes in v3:
- Assign NULL to *controller so it remains that i
I am trying to build Uboot for Nios2.
I do the following on Linux bash.
> git clone git://git.denx.de/u-boot-nios.git
> cd u-boot-nios/
> make menuconfig
These proceeding steps complete with no visible errors or warnings.
> make all
This step fails with the following error
LD arch/nio
On 12 August 2015 at 20:16, Simon Glass wrote:
> Hi,
>
> On 11 August 2015 at 11:41, Simon Glass wrote:
>> Hi Stephen,
>>
>> On 11 August 2015 at 11:33, Stephen Warren wrote:
>>>
>>> On 08/11/2015 08:33 AM, Simon Glass wrote:
This is a convenient way for a driver to get the hardware ad
Hello,
Reply in-line
Op 17-08-15 om 08:34 schreef Boris Brezillon:
Hi Oliver,
Sorry for the late reply (I was in vacation for the last 2 weeks)
On Tue, 11 Aug 2015 14:16:52 +0200
Olliver Schinagl wrote:
Hello everybody,
We are working with Boris and Roy's patch series on getting the NAND
2015-08-12 7:31 GMT+09:00 Masahiro Yamada :
> We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing
> devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
> away the ugly logic in include/fdtdec.h:
>
> #ifdef CONFIG_OF_CONTROL
> # if defined(CONFIG_SPL_BUILD) && !defined
I found some of my boards would not boot since commit 2afddae07523
("Align global_data to a 16-byte boundary"). Probably, many ARM
boards using Generic Board framework are broken, including ARM64
ones. That commit aligned the global data pointer, i.e. inserted
some spaces between the gd and the b
Hi Bin,
On 08/07 08:11, Andrew Bradford wrote:
> Hi Bin,
>
> On 08/07 08:23, Bin Meng wrote:
> > Hi Andrew,
> >
> > On Fri, Aug 7, 2015 at 4:08 AM, Andrew Bradford
> > wrote:
> > > From: Andrew Bradford
> > >
> > > Allow for configuration of FSP UPD from the device tree which will
> > > overri
Hi Andrew,
On Mon, Aug 17, 2015 at 8:51 PM, Andrew Bradford
wrote:
> Hi Bin,
>
> On 08/07 08:11, Andrew Bradford wrote:
>> Hi Bin,
>>
>> On 08/07 08:23, Bin Meng wrote:
>> > Hi Andrew,
>> >
>> > On Fri, Aug 7, 2015 at 4:08 AM, Andrew Bradford
>> > wrote:
>> > > From: Andrew Bradford
>> > >
>> >
Added zynq qspi controller driver for Xilinx Zynq APSOC,
this driver is driver-model driven with devicetree support.
=> sf probe
SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total
16 MiB
=> mw.b 0x100 0xCC 0x100
=> sf update 0x100 0x0 0x100
device 0 whole chip
1
Enabled zynq qspi controller node for microzed board,
verified the same on spansion spi-nor flash.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Jagan Teki
---
arch/arm/dts/zynq-microzed.dts | 5 +
1 file changed, 5 insertions(+)
di
These are the last two version patches links.
https://patchwork.ozlabs.org/patch/302945/
https://patchwork.ozlabs.org/patch/264440/
This series adds zynq qspi controller driver in driver model and
enabled support on relevent zynq boards and tested the same.
Branch to verify:
$ git clone git://git
This patch adds zynq qspi controller nodes in zynq-7000.dtsi.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Jagan Teki
---
arch/arm/dts/zynq-7000.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/dts/zynq-70
Enabled zynq qspi controller node for zc702 board.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
arch/arm/dts/zynq-zc702.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index
Added device-tree-binding information for zynq qspi controller
driver.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Jagan Teki
---
doc/device-tree-bindings/spi/spi-zynq-qspi.txt | 26 ++
1 file changed, 26 insert
Enabled zynq qspi controller node for zc706 board.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
arch/arm/dts/zynq-zc706.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index
Enabled zynq qspi controller node for zc770-xm010 board.
=> sf probe 0 -- bus0 for selecting spi controller
=> sf probe 1 -- bus1 for selecting qspi controller
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
arch/arm/dts/zynq-zc770-xm010.dts | 5
Enable legacy spi-flash interface support for boards which
supports qspi controller with connected spi-nor flash.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Jagan Teki
---
configs/zynq_microzed_defconfig | 1 +
configs/zynq_zc702_defc
Enable zynq qspi controller driver on respective zynq boards.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Jagan Teki
---
configs/zynq_microzed_defconfig| 1 +
configs/zynq_zc702_defconfig | 1 +
configs/zynq_zc706_defconfig
Add Zynq QSPI controller Kconfig entry.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
drivers/spi/Kconfig | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c84a7b7..facd94d 100644
--- a/
This patch adds support for zynq qspi controller driver
on zynq-common.h
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Jagan Teki
---
include/configs/zynq-common.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/conf
Enabled zynq qspi controller node for zed board.
Signed-off-by: Jagan Teki
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
---
arch/arm/dts/zynq-zed.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 5762576
Enabled SPI flash Bank/Extended address register support.
Bank/Extended address registers are used to access the flash
which has size > 16MiB in 3-byte addressing.
Signed-off-by: Jagan Teki
---
include/configs/zynq-common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/zyn
Update the numerical values for baudrate and chipselect
with config reg shift named macro's
Signed-off-by: Jagan Teki
---
drivers/spi/zynq_spi.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index b9cf335..817728c 1
Store cs value into private data and use it while activating
chipselect instead of passing through function.
Signed-off-by: Jagan Teki
---
drivers/spi/zynq_spi.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 70d7
Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK
for more readable.
Signed-off-by: Jagan Teki
---
drivers/spi/zynq_spi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 817728c..70d7716 100644
--- a/drivers/spi/zyn
On Fri, Aug 14, 2015 at 10:57:59AM -0600, Simon Glass wrote:
> Hi Tom,
>
> This includes various fixes including moving x86 over to use
> board_init_f_mem() and proper interrupt support on minnowmax. The
> revert of fdtdec_get_addr_size() is here also. Stephen confirmed it
> will not affect 64-bi
On Thu, Aug 13, 2015 at 09:51:00AM -0500, Nishanth Menon wrote:
> DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
> provided IODELAY values for standard RGMII phys do not work.
>
> Silicon Revision(SR) 2.0 provides an alternative bit configuration
> that allows us to do a "gro
On Thu, Aug 13, 2015 at 09:50:58AM -0500, Nishanth Menon wrote:
> Add support for detection of ES2.0 version of DRA7 family of
> processors. ES2.0 is an incremental revision with various fixes
> including the following:
> - reset logic fixes
> - few assymetric aging logic fixes
> - MMC clock rate
On Thu, Aug 13, 2015 at 09:50:59AM -0500, Nishanth Menon wrote:
> Silicon revision 2.0 has new signal routing hence has an updated set of
> iodelay parameters to be used. Update the configuration for the same.
> Padmux remains the same.
>
> Based on data from VayuES2_EVM_Base_Config-20150807.
>
For accessing SPI-NOR flash's with > 16MiB we have two choices like
Bank/Extended and 4-byte addressing register support.
Status in u-boot:
1) BAR (Bank/Extended)
- Added support in u-boot already, tested
2) 4-byte addressing
- No support yet
- Hou Zhiqiang sent patches, those are review.
Ideall
Currently u-boot stack is defined at the beginning of MSMC RAM.
This is a problem for uart boot mode as ROM downloads directly to
starting of MSMC RAM.
Fixing it by moving stack to the end of u-boot section and shifting
SYS_TEXT_BASE to the start of MSMC RAM.
Updated division of MSMC RAM is shown b
From: Nishanth Menon
Keystone has build rules introduced by commit ef509b9063fb7 ("k2hk: add
support for k2hk SOC and EVM") and commit 0e7f2dbac6ead ("keystone: add
support for NAND gpheader image").
These are not reused by other platforms for the build, hence there is no
clear benefit is mainta
Currently we need to build each image(u-boot.uart, u-boot-nand.gph,
u-boot-spi.gph) separately for all keystone2 platforms.
This series does the following:
- Move SP to end of u-boot section so that u-boot.bin can be used as
build target for uart boot.
- Renames u-boot-nand.gph to MLO so that th
MLO(NAND/MMC boot image), is used for all the ks2 platforms.
Enabling it in config.mk so that these images will be automatically
built upon calling make. u-boot-spi.gph is already the build target,
so not including here.
Reported-by: Nishanth Menon
Reviewed-by: Nishanth Menon
Signed-off-by: Loke
NAND boot mode, ROM expects an image with a gp header in the
beginning and an 8bytes filled with zeros at the end. The same is
true for SD boot on K2G platforms but the file name should be MLO.
Renaming u-boot-nand.gph to MLO, so that same image can be used for
NAND and SD boots. And also not incl
Update README to include uart boot mode support and makefile
changes.
Signed-off-by: Lokesh Vutla
---
board/ti/ks2_evm/README | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README
index b824725..b8d55e7
201 - 300 of 403 matches
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